An Efficient Design Space Exploration Methodology for Multiprocessor SoC Architectures based on Response Surface Methods Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria Politecnico di Milano Dipartimento di Elettronica e Informazione Via Ponzio 34/5, 20133 Milano - Italy E-mail: {gpalermo.silvano.zaccaria}@elet.polimi.it Abstract-Multi-Processor System on-Chip (MPSoC) architec- tures are currently designed by using a platform-based approach. In this approach, a wide range of platform parameters must be tuned to find the best trade-offs in terms of the selected figures of merit (such as energy, delay and area). This optimization phase is called Design Space Exploration (DSE) and it generally consists of a Multi-Objective Optimization (MOO) problem. The design space for an MPSoC architecture is too large to be evaluated comprehensively. So far, several heuristic techniques have been proposed to address the MOO problem for MPSoC, but they are characterized by low efficiency to identify the Pareto front. In this paper, an efficient DSE methodology is proposed leveraging traditional Design of Experiments (DoE) and Response Surface Modeling (RSM) techniques. In particular, the DoE phase generates an initial plan of experiments used to create a coarse view of the target design space; a set of RSM techniques are then used to refine the exploration. This process is iteratively repeated until the target criterion (e.g. number of simulations) is satisfied. A set of experimental results are reported to trade-off accuracy and efficiency of the proposed techniques with actual workloads l • I. INTRODUCTION In the recent years, Multi-Processor Systems-on-Chip (MP- SoC) and Chip-Multi-Processors (CMPs) have become the de facto standard for embedded and general-purpose architec- tures. The platform-based design methodology [1] represents the winning paradigm to design optimized architectures and meeting time-to-market constraints. In this context, parametric System on-Chip (SoC) simulation models are built and eval- uated to accurately tune the architecture to meet the target application requirements in terms of performance, battery lifetime and area. This tuning phase is called Design Space Ex- ploration (DSE) and it generally consists of a multi-objective optimization problem. The problem is generally solved by ex- ploring a large design space consisting of several parameters at system and micro-architectural levels. So far, several heuristic techniques have been proposed to address this problem, but they are characterized by low efficiency to identify the Pareto front. Evolutionary or sensitivity based algorithms are among the most notable, state-of-the art techniques. In this paper, we propose an iterative design space ex- ploration methodology exploiting traditional Design of Ex- lThis work was supported in part by the EC under grant MULTICUBE FP7-216693 978-1-4244-1985-2/08/$25.00 ©2008 IEEE periments (DoE) and Response Surface Modeling (RSM) techniques. First, the DoE phase generates an initial plan of experiments used to create a coarse view of the target design space; then a set of RSM techniques are used to refine the exploration. This process is iteratively repeated until a target criterion (e.g. number of simulations) is satisfied. The proposed methodology is highly flexible because, in principle, any combination of DoE and RSM techniques can be used. However, from the analysis of the experimental results carried out in the paper with actual workloads, two guiding strategies (low-end and high-end) have been identified. From one side, the low-end strategy combines a DoE generated randomly to a linear regression model to obtain a less accurate but very efficient exploration. From the other side, the high- end strategy combines more sophisticated DoE and RSM techniques to obtain accuracy/efficiency trade-offs. To the best of our knowledge, although there have already been some applications of DoEs and RSM techniques to the field of performance analysis and optimization, the work proposed in this paper represents the first in-depth, compre- hensive application of DoE and RSM techniques to the field of multi-objective design space exploration for on-chip multi- processors. The paper is organized as follows. Section II discusses the state of the art related to design space exploration while Section III introduces a formalization of the problem of the design space exploration. Section IV introduces the design space exploration methodology proposed in this paper, while Section V reports the experimental results derived from the application of the proposed methodology on a general-purpose multiprocessor platform. II. STATE OF THE ART Several methods have been recently proposed in literature to reduce the design space exploration complexity by using traditional statistic techniques and advanced exploration algo- rithms. The proposed techniques can be partitioned mainly in two categories: heuristics for architectural exploration and methods for the system performance estimation and optimiza- tion. Among the most recent heuristics for power/performance architectural exploration we can find [2]-[4]. In [2], the 150