Two-Levels of Adaptive Buffer for Virtual Channel Router in NoCs Caroline Concatto 1 , Anelise Kologeski 1 , Luigi Carro 1 and Fernanda Kastensmidt 1 1 Informatics Institute, Federal University of Rio Grande do Sul, Porto Alegre, Brazil {cconcatto, alkologeski, carro, fglima}@inf.ufrgs.br Gianluca Palermo² and Cristina Silvano² Politecnico di Milano, Milan, Italy Department of Electronics and Information {gpalermo silvano}@elet.polimi.it Abstract - NoC designs are based on a compromise of latency, power dissipation or energy, usually defined at design time. However, setting all parameters at design time can cause either excessive power dissipation (originated by router underutilization), or a higher latency. Moreover, routers with virtual channels have larger buffer sizes and more complex control, increasing the total costs. The situation worsens whenever the application changes its communication pattern, i.e., when a portable phone downloads a new service. In this paper we propose the use of a two-level adaptive buffer for a virtual channel router, where the buffers units and the virtual channels are dynamically allocated to increase router efficiency in a NoC, even under rather different communication loads. With the proposed architecture the buffer and virtual channels in the input channels of the routers can be adapted at run time. The adaptive virtual channel router decreases the latency in the worst case by 10%, and a reduction of 80% in the best case is achieved when compared to previous works. Keywords- Network-on-Chip, Buffer, Depth, virtual channel, Latency, Throughput, Adaptability I. INTRODUCTION Multiprocessor System-on-Chip (MPSoCs) are emerging as one of the technologies providing a way to support the growing design complexity of embedded systems, since they provide processor architectures adapted to selected problem classes, allied to programming flexibility. To ensure flexibility and performance in the future, MPSoCs will combine several types of processors cores and data memory units of widely different sizes, leading to a very heterogeneous architecture. The increasing interconnection complexity and the known scalability deficiency of buses require another model of interconnection. The communication among cores of an MPSoC having reusable and scalable interconnections is being provided by Networks-on-Chip (NoC) [1]. NoCs have been proposed to integrate several IP (Intellectual Property) cores providing high communication bandwidth and parallelism. NoC are basely composed of routers, network interfaces and links. The router contains buffers, flow controllers and crossbar. Buffers are the instrumental elements in router input channels. They consume about 64% of the total router leakage power [2], making them the largest source of leakage energy consumed in NoCs. Moreover, in terms of dynamic energy consumption, buffers are dominant [2]. The work in [3] shows that the router consumes more energy to store the flits than to transmit them. Hence, the effective and resourceful management of buffers in NoC routers has a significant impact in performance and efficiency of interconnection networks. The design of a NoC can be done in a huge design space, where the number of Virtual Channel (VCs) per channel and the buffer size for each VC are the two main parameters that influence in the utilization, throughput and latency of the NoC. Detailed studies in [9] have shown that the relation between virtual channels and network latency indicates that for low traffic intensity, a small number of VCs can be enough. Under high injection rates, however, increasing the number of VCs is more effective to improve performance than only increasing the buffer depth. Under light network traffic, the number of packets traveling through a NoC is small enough to be accommodated by a limited number of VCs. Under high injection rates, many packets want to use the channel at the same time; increasing VC depth will not alleviate this contention. Increasing the number of VCs and the buffer size of each virtual channel, though, will allow more packets to share the physical channels. This study in VC organization implies that routers with fixed buffer structures will either be underutilized or will underperform under certain traffic conditions. In this work, we propose a NoC router architecture that enables two levels of reconfiguration: i) dynamic reconfiguration of the buffer size for each channel and ii) dynamic reconfiguration of each virtual channel. The first level is done through the loan of buffers from the neighbor ports in the router. The second level is done through the use of dynamic allocation of the virtual channels. Our proposed architecture tries to alleviate the effect of congestion in a NoC. Intuitively, the crux of our design is in the effective usage of available buffers and virtual channels to increase performance. The paper also proposes a router architecture implementing the proposed two-level adaptive buffers and VCs reconfiguration. Comparison results with the ViChaR router architecture proposed in [5] are reported for Mpeg4 and VOPD applications showing performance, power and area tradeoffs. This paper is organized as follows. In section 2 we present some related works that show the need for reconfiguration after fabrication. The adaptive router is proposed in section 3, where we describe the new architecture. In section 4 we present and analyze some synthesis and performance results and finally the conclusions are described in section 5. 978-1-4577-0170-2/11/$26.00 ©2011 IEEE 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip 302