Multi-Bias Dependence of Threshold Voltage, Subthreshold Swing, and Mobility in G 4 -FETs K. Akarvardar 1 , B. Dufrene 2 , S. Cristoloveanu 1 , B. J. Blalock 2 , T. Higashino 1 , M. M. Mojarradi 3 , and E. Kolawa 3 1 Institute of Microelectronics, Electromagnetism, and Photonics (UMR CNRS) ENSERG, Grenoble, France 2 Department of Electrical and Computer Engineering, The University of Tennessee, Knoxville, TN; USA 3 Avionic Equipment Section, Jet Propulsion Laboratory Pasadena, CA; USA Abstract: Systematic measurements in four-gate SOI transistors (G 4 - FET) are presented. Methods of extraction for the thres hold voltage, subthreshold swing, and mobility in the linear region are discussed and results are shown. The extracted parameters demonstrate the complex dependence of the multi-gate biases, which is explained. A new extraction technique for the carrier mobility and effective width of devices with isolated multiple gates is proposed. 1. Introduction The G 4 -FET is a novel accumulation-mode SOI transistor, introduced in [1], which combines two vertical MOS gates and two lateral junction gates to surround and control the channel (insert of Fig. 1). The device uses no additional process steps because it is fabricated using the structure of a conventional partially depleted MOSFET . Two additional body contacts (source and drain) are perpendicular to either side of the conduction flow of the traditional MOSFET. The G 4 -FET’s junction gates are identical and were biased to the same potential (V JG ) in all measured results. The top gate potential (V G1 ) and bottom gate potential (V G2 ) were biased to different potentials due to the different oxide thicknesses. Preliminary current-voltage characteristics, show - ing the modulation provided by either the MOS gates or the junction gates have been presented at ESSDERC’02 [2] and supported by 2-D simulations. In the present work, we propose a more advanced analysis of the device parameters. The thres hold voltage, subthreshold swing, and mobility (viewed from the top gate or from the lateral gates ) are determined and discussed with the other gate biases as parameters. The results are explained using physics-based models of the G 4 -FET as well as 3-D simulations. 2. Parameter Extraction Parameter extraction was based on the idea of three different channel regions (front channel, back channel, and neutral volume), which can be activated by multi-biased measurements of the G 4 -FET. Fig. 1a shows typical measured characteristics of drain current as a function of back gate bias with the top gate in accumulation (+1V), depletion (0V), and inversion (-3V). For positive front gate bias the channel cannot be turned off. Similar curves are obtained by plotting the current versus top gate or junction gate bias. Simulated characteristics (with Silvaco tools) are displayed in Fig. 2. From such characteristics the key device parameters can be uncovered. 10 -12 10 -11 10 -10 10 -9 10 -8 10 -7 10 -6 10 -5 10 -4 -40 -30 -20 -10 0 10 20 30 40 I D (A) V G2 (V) V G1 =1V V G1 =0V V G1 =-3V (a) -2 10 -5 0 10 0 2 10 -5 4 10 -5 6 10 -5 8 10 -5 -40 -30 -20 -10 0 10 20 30 40 d 2 I D /dV G2 2 (AV -2 ) V G2 (V) Top Channel Middle Channel Bottom Channel (b) Fig. 1. (a) Drain current versus back gate bias with VJG=-1V. (b) Double derivative method: the peaks indicate the activation of the three channels for the G 4 - FET (V JG =-1.2V, V G1 =1.1V, and V DS =50mV).