FULLY PROGRAMMABLE BIAS CURRENT GENERATOR WITH 24 BIT RESOLUTION PER BIAS Tobi Delbrück, Patrick Lichtsteiner, Inst. of Neuroinformatics,UNI-ETH Zürich, Switzerland ABSTRACT This paper describes an on-chip programmable bias current generator, intended for mixed signal chips requiring a wide ranging set of currents. The individual generators share a master current reference. A serial digital interface to the chip controls the biases by bits loaded into a 24-bit shift register. These bits control the steering of current from a current splitter. The summed current splitter output is actively mirrored to a broadcasted bias voltage. Measurements from an implementation in 0.35u 4M-2P CMOS show a total range of bias current of over 6 decades (>120dB) ranging from a few times the off-current up to the master reference current. For currents larger than the minimum, the generator has resolution spanning nearly its full 24 bit range (144dB), e.g. for a master current of 10uA, any bias current can be varied by as little as 0.5 pA with the caveat that the code is not guaranteed monotonic. Each bias occupies an area of 0.026 mm 2 , which is about 65% of the bonding pad that it replaces. Measured variation in generated currents is <10% in strong inversion and about 20-30% in weak inversion. 1. INTRODUCTION We earlier reported a design kit for generating wide ranging fixed bias currents [1, 2]. These circuits compact and are suitable for chips with known biasing requirements for very wide ranging currents, when the fixed currents need only be resolved to within the nearest factor of two. However it is often the case with complex chips that the required currents are not known ahead of time or that they need to be changed during operation. In general it is desirable to avoid any off-chip analog components, especially if they require high precision. Using off-chip voltage DACs that drive gate voltages is an interim solution to programmability. It is a very poor solution if one considers the cost in pin count, temperature and process sensitivity, board complexity, and cost. Here we report a completely programmable integrated bias current generator with a simple digital interface. 2. IMPLEMENTATION The system level diagram is shown in Fig. 1. A microcontroller (uC) interfaces between the chip and a controller PC. The SPI (Serial Peripheral Interconnect) interface to the bias generator uses 3-8 wires, depending on desired functionality and testability. At a minimum, Clock, IN, and Latch input are required. We also use the master bias power-down input Power-down to turn off all currents and we generally use an off-chip resistor R master instead of the integrated resistor, bringing the total to 5 pads. Other pads provide access to the master bias voltage gate voltage and to n- and p-type test transistor gate and drain terminals. Shift register output OUT can be tied to the next chip in series, if desired. As before [1, 2], we assume that the design requires a fixed transconductance, rather than a fixed current or precise reference voltage. All biases are controlled by a single Sivilotti-type [3] single-phase register (SR); each bias uses 24 bits of the shift register to steer the current in a 24-bit octave current splitter [1, 2, 4]. The input to each current splitter is a copy of the master bias current I m . Thus each bias can in principle be any fraction of up to 24 bit resolution of the master current. Level-sensitive latches (L) are made opaque (Latch high) while new bias settings are loaded and then transparent to transfer the SR outputs to the current multiplexer switches. The output from the splitter is steered to a dual n- and p-type ‘current buffer’ (CB) consisting of two active mirrors, which serve to isolate the splitter from the rest of the chip and to greatly lower the bias voltage impedance [1, 5]. The buffers are biased with the master current. The outputs of the buffers are the n-bias and p-bias voltages that are used in the chip core. These circuits were fabricated in the AMS 0.35u 4M-2P process as part of a vision sensor chip with 12 biases. Fig. 2 shows a micrograph of the entire generator and layout of a single splitter cell. Common centroid layout was not used but may improve splitter ratio matching. Dummy splitter cells at the ends were used, and metal coverage of the splitter transistors was made as identical as possible. A complete 12-bias layout in 0.35u occupies an area of 0.63 mm 2 , or about 13% of a minimum sized Europractice or MOSIS design. Each individual bias has an area of 0.026 mm 2 —about 65% of the bonding pad it could replace. A Windows XP software infrastructure was built to interface transparently to either a Cypress FX2 USB2