Selected best papers from ETS’06 Improving high-level and gate-level testing with FATE: A functional automatic test pattern generator traversing unstabilised extended FSM G. Di Guglielmo, F. Fummi, C. Marconcini and G. Pravadelli Abstract: A functional automatic test pattern generator (ATPG) that explores the design under test (DUT) state space by exploiting an easy-to-traverse extended finite state machine (FSM) model has been described. The ATPG engine relies on learning, backjumping and constraint logic program- ming to deterministically generate test vectors for traversing all transitions of the extended FSM. Testing of hard-to-detect faults is thus improved. The generated test sequences are very effective in detecting both high-level faults and gate-level stuck-at faults. Thus, the reuse of test sequences gen- erated by the proposed ATPG allows also to improve the stuck-at fault coverage and to reduce the execution time of commercial gate-level ATPGs. 1 Introduction Many economical and practical reasons have induced the designers to start automatic test pattern generation at high abstraction levels [1, 2]. In this way, the verification of complex systems is more tractable and design errors can be identified early and removed, saving time and money. Thus, many high-level automatic test pattern generators (ATPGs) have been proposed to generate effective test sequences [3–9]. On the other side, gate-level ATPGs rep- resent the state-of-the-art for digital system testing [10 – 13]. However, they pay the achieved good fault coverage results in terms of time and required resources. In this paper, we propose an high-level ATPG framework which is fast, since it relies on simulation, but also very effective in covering corner cases, since it uniformly explores the state space of the design under test (DUT). The proposed ATPG has been primarily intended for func- tional verification to detect design errors early. However, it can be exploited to improve gate-level testing too. In fact, the test sequences generated by the proposed ATPG reveal to be very effective to cover gate-level stuck-at faults. Experimental results show how stuck-at coverage achieved by reusing high-level test sequences is comparable with stuck-at coverage achieved by a state-of-the-art com- mercial gate-level ATPG. Moreover, in a hierarchical testing context, the commercial ATPG benefits by simulat- ing functional test sequences before applying its generation engines, since this increases fault coverage and decreases execution time. The development of a functional ATPG requires to deal with four basic aspects: (a) the formalism used to model the DUT, (e.g. FSM [7], assignment decision diagram [4, 8], BDD [3], etc.); (b) the algorithm to take decisions to move from a state to another one during DUT state exploration (e.g. genetic algorithms [14], SAT-solving [8], constraint logic programming [9], linear programming [8], etc.); (c) the strategy to deterministically reach particular states of the DUT representing corner cases (e.g. learning [15], justification [7], backtracking [4], back-jumping [16], etc.); (d) the metrics to evaluate the quality of gener- ated test sequences (transition coverage [17], path coverage [18], statement coverage [18], fault coverage [3], etc.). In this context, the paper presents the functional ATPG FATE which addresses the previous aspects as follows (Fig. 1): (a) The extended FSM (EFSM) paradigm is used to model the DUT. In particular, FATE works on a special kind of EFSM whose transitions present a quite uniformly distribu- ted probability of being deterministically traversed [19]. (b) A constraint logic programming-based (CLP) strategy is adopted to deterministically generate test vectors that satisfy the guard of the EFSM transitions selected to be traversed. (c) A two-step ATPG engine is implemented which exploits CLP to traverse the DUT state space: first, a random walk-based approach is used to cover the majority of easy-to-traverse (ETT) transitions; then a backjumping- based mode is used to activate hard-to-traverse (HTT) tran- sitions. In both modes, learning is exploited to get critical information that improves the performance of the ATPG. (d) Transition coverage is used to verify the goodness of our ATPG, since 100% transition coverage represents a necessary condition for fault coverage and for more accu- rate coverage metrics. Then, we have adopted the high-level bit coverage fault model [20], to measure the functional coverage of the generated test sequences, which have been also simulated at gate-level on stuck-at faults to check fault coverage on logic-level implementations. To summarise, the main contribution of the paper consists of proposing a functional ATPG targeted to: † generate functional test for multiprocess DUTs; † exploit the EFSM model to guide a CLP-based solver during the DUT traversal; # The Institution of Engineering and Technology 2007 doi:10.1049/iet-cdt:20060139 Paper first received 31st August 2006 and in revised form 22nd February 2007 The authors are with the Dipartimento di Informatica - Universita ` di Verona, Strada Le Grazie 15, Verona 37134, Italy E-mail: marconcini@sci.univr.it IET Comput. Digit. Tech., 2007, 1, (3), pp. 187–196 187