Analytical Modeling of Read Stability Metric of SRAM Cell in Nanoscale era Behzad Ebrahimi, Hossein Aghababa, and Ali Afzali-Kusha Nanoelectronics Center of Excellence, School of Electrical and Computer Engineering, University of Tehran Tehran, Iran Abstract—In this paper, we propose an analytical model for read stability metric (read margin) of sub-45nm SRAM cells. First, analytical expressions for V read and V trip of the cell are derived. The expressions are obtained using a simple model for the I-V characteristics of the transistors valid for sub-45nm technologies. The I-V model, which is based on the n-th power model, has integer powers of voltage. The accuracy of the analytical model is verified by comparing its results with those of HSPICE simulations. The results show a very good accuracy for the proposed model for a wide range of transistor sizes. The accuracy of the models is also verified in the presence of threshold voltage fluctuations. Keywords- Modeling; Read Stability; SRAM; Sub 45-nm. I. INTRODUCTION Analytical I-V models may be used during the design of integrated circuits. In nano-scale regime, simple square law model for the I-V characteristic of MOSFET is not valid because of second order effects such as velocity saturation and short channel effects. There have been many efforts for presenting models for the characteristics of these transistors including these effects (see, e.g., [1], [2]). These models most often become complicated prohibiting their use for analytical calculations required for some design optimization. Simple models with high accuracies also have been developed for the circuit analysis. The n-th power model [3], [4] is an example of these simple models. Added to the complexity of modeling transistors is the variation of device parameters due to process variations. Scaling has led to a severe increase in the variations whose examples include random-dopant fluctuations and channel length variations. The variations along with the scaling of the supply and threshold voltages degrade the stability of conventional six- transistor (6-T) SRAM cells [5]. Vulnerability to the variation in the read state is one of the most important issues that may decrease the yield. Read stability can be measured using read Static Noise Margin (SNM) [6] or read margin [7]. In [8]-[10], the read SNM has been modeled. The models in these works, however, are complex or implicit. In [11], a model for the read margin has been proposed. The accuracy of this model which uses the simple square law I-V model is questionable. In this work, we present an approach for analytical modeling of the read margin of conventional 6T SRAM cells based on sub-45nm MOSFETs. The rest of the paper is organized as follows. In Section II, the read stability metric for a SRAM cell is described. In Section III, first a simple I-V model for sub- 45nm MOSFET transistors are proposed and then analytical expressions for V read and V trip are derived. In Section IV, the accuracy of the model for different transistor sizes and threshold voltages are discussed. Finally, Section V concludes the paper. II. READ STABILITY METRIC A conventional SRAM cell is schematically shown in Fig. 1. For read operation, BL and BLC are precharged to V dd and then WL is activated. Read operation is performed when a pre- specified voltage difference (e.g., min  0.1V dd ) between the two bitlines of the cell is produced. But due to the voltage division between the right access transistor (AR) and the right pull down transistor (NR), the voltage at the right node (VR) increases to a positive value denoted by V read . If V read is higher than the trip point of the left inverter (PL - NL), named as V trip , then the cell flips while reading the cell and a read failure occurs (see Fig. 2). We should design SRAM cell so that V trip becomes higher than V read even in the presence of noise and process variations. The read margin defined as V trip – V read may be considered as a good metric for the read stability of the cell [7]. The minimum needed read margin depends on the environment that the memory cell works. In noisy areas this value is larger. These two voltages can be found analytically from the KCL equations at the storage nodes [11]. V trip can be found by using the KCL equation at the node L when VL and VR are set to V trip as [11] ) , 0 , ( trip d s trip g NL Dsat V V V V V I = = = - ) , , ( trip d dd s trip g PL Dsat V V V V V V I = = = = - ). , , ( dd d trip s dd g AL Dsat V V V V V V I = = = + - (1)            Figure 1. Conventional 6T SRAM cell (VL= “1” and VR= “0”). 978-1-4244-9996-0/10/$26.00 ©2010 IEEE 2010 IEEE International Conference of Electron Devices and Solid-State Circuits (EDSSC)