Design of a binary-weighted resistor DAC using tunable linearized floating-gate CMOS resistors Erhan ¨ Ozalevli, H¨ useyin Dinc ¸, Haw-Jing Lo, and Paul Hasler School of Electrical and Computer Engineering Georgia Institute of Technology, Atlanta, Georgia 30332–0250 Abstract— We present an implementation of a 4 - bit binary- weighted-resistor DAC to be used in quantizers. It is built by using tunable floating-gate CMOS resistors, which exploit the capacitive coupling and voltage storage capabilities of floating- gate transistors and employ scaled-gate linearization technique to suppress the MOSFET nonlinearities. The resistance of these resistors drifts 1.6 · 10 -3 % over the period of 10 years at 25 o C. By using these resistors, 15 - bit accurate DAC is implemented in 0.5μm CMOS process. I. I NTRODUCTION In multi-bit-per-stage pipelined and sub-ranging converters as well as in oversampling converters, multi-bit quantizers can be successfully employed to improve the overall performance. In pipelined ADCs, the use of multi-bit quantizers decreases the number of stages and reduces the conversion latency. Also, interstage analog signal processing performance can be optimized depending on the accuracy of the sub-stages. Proper selection of stage resolution and use of multi-bit quantizers allow for the optimization of silicon area, power consumption, and conversion speed for resolutions higher than 10 bits [1]. Similarly, multi-bit quantizers are important in building oversampling converters. When designing a converter with a high dynamic range for the low-voltage and low-power applications, the signal swing at the integrator output needs to be lowered, and this requirement can be readily met by employing multi-bit quantizers. Also, increasing the number of bits of the internal quantizer in ΔΣ modulators enables for the reduction of the quantization noise by 6dB for each additional bit, and improves the stability of the higher order ΔΣ modulators [2] [3]. A quantizer can be easily built by using a binary-weighted resistor DAC structure. Although this kind of DAC structure can be fast and insensitive to parasitics, it is susceptible to resistor mismatches, which can substantially alter the linearity performance of the converter. Passive resistors in CMOS tech- nologies are typically implemented by utilizing polysilicon, diffusion or well strips. These resistors exhibit around ±0.1% matching accuracy and ±30% tolerance due to device-to- device and lot-to-lot variations in semiconductor fabrication processes [4]. Thin film resistors typically have much better matching accuracy and temperature coefficients, but they are not available in the main stream CMOS processes. The device mismatches and component variations in CMOS processes are generally minimized by employing calibration methods. These calibration techniques include trimming and the use of b 3 V out V c b 2 b 1 b 0 R c R f R 0 R 1 R 2 R 3 V ref Fig. 1. Proposed implementation of a binary-weighted DAC using tunable resistors. R i is the tunable resistor, where i =0, 1, 2, 3. Also, R f is the feedback resistor, and Rc is used to obtain the full output voltage range and to tune the offset of the DAC. Vc is set to supply rail of the DAC. programmable binary-weighted array. Component trimming is achieved during the test phase of the production by using laser technology. The programming method is used to choose the desired array of elements by blowing fuses. These methods are irreversible and introduce problems over time due to aging, stress, and temperature. In this paper, we propose a design of a linearized tunable floating-gate CMOS resistor to be incorporated into binary- weighted resistor DAC. This tunable resistor is implemented in a standard CMOS process and provides high resolution and precise device calibration through the use of floating- gate transistors. In contrast to previously reported floating-gate CMOS resistors [5], [6], this resistor has a simple structure and provides a high degree of design flexibility in optimizing the overall area and the tuning range of the resistance. In the next section, we describe the design and implementation of the binary-weighted resistor DAC. After that we explain the design and implementation of the tunable linear floating-gate resistor (FGR), and analyze its temperature dependence. Subsequently, we present the experimental results of these circuits. II. DESIGN AND IMPLEMENTATION OF RESISTIVE DAC The binary-weighted resistor DAC structure is depicted in Figure 1. Variable resistors are used to obtain the scaled currents and full output voltage swing at the DAC output. The input resistors, R i , switch between ground and voltage reference, V ref , and generate the scaled currents. Also, V c and R c are used to obtain a larger output voltage range by creating an offset current. In addition, due to tunability of these resistors, R c enables to tune the offset of the DAC. IEEE 2006 Custom Intergrated Circuits Conference (CICC) 1-4244-0076-7/06/$20.00 ©2006 IEEE 149 8-2-1