936 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 18, NO. 7, JULY 1999 VHDL Semantics and Validating Transformations Sheetanshu L. Pandey, Kothanda Umamageswaran, and Philip A. Wilsey, Senior Member, IEEE Abstract—Formal models are used to provide an unambiguous definition of the semantics of very high speed integrated circuit hardware description language (VHDL) and to prove equiva- lences of VHDL programs. This paper presents a formal model of the dynamic semantics of VHDL that characterizes several important features of VHDL such as delta delays, pulse rejec- tion limits, disconnection delays, postponed processes, sequential statements, and resolution functions. The underlying logic is interval temporal logic, which assists in characterizing the timing information contained in a VHDL program. The semantic definition is not dependent on the VHDL sim- ulation cycle since it only defines the net effect of evaluating a VHDL program. It is argued that this declarative style coupled with the inherent advantages of temporal logic makes it possible to validate transformations (or rewrite rules) on VHDL programs and to formally reason about the timing aspects of VHDL. In particular, we present proofs of soundness of rewrite rules such as process folding and signal collapsing, and use temporal logic to derive an algorithm for determining when a given VHDL program is free of transaction preemption. Index Terms— Formal semantics, simulator optimizations, VHDL. I. INTRODUCTION H ARDWARE Description Languages (HDL’s) provide an efficient mechanism to specify and verify hardware designs prior to fabrication. computer-aided design (CAD) tools based on HDL’s have, to some extent, automated the process of design verification. A common methodology for verifying designs is to simulate a model of the design (written in an HDL) and verify its functionality by comparing the simulator outputs against the expected outputs. A more recent technique is to directly synthesize a circuit from a high-level HDL specification of its behavior. The synthesized circuit is assumed to be “correct by construction” if the transformation rules used by the synthesis tools can be shown (or formally proven) to be sound. In order to develop correct and consistent CAD tools for HDL’s, an unambiguous formal definition of their semantics is needed. In particular, there is interest in the formalization of the semantics of very high speed integrated circuit hardware description language (VHDL) since it has come to be accepted as a standard HDL. Formal semantic definitions also provide a basis for 1) proving the soundness of transformation rules on Manuscript received April 30, 1998; revised October 6, 1998. This work was supported in part by the Defense Advanced Research Projects Agency and monitored by the Air Force Wright Laboratory under Contract F33615- 93-C-1315. This paper was recommended by Associate Editor D. Dill. S. L. Pandey is with Synopsys, Inc., Mountain View, CA 94043 USA. K. Umamageswaran is with Oracle Corporation, Redwood Shores, CA 94065 USA. P. A. Wilsey is with the Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati, Cincinnati, OH 45221 USA. Publisher Item Identifier S 0278-0070(99)05032-0. VHDL programs, 1 2) proving the equivalence of two VHDL descriptions that describe the same design at different levels of abstraction, 2 and 3) checking the properties of VHDL descriptions using model-checking [1] techniques. The VHDL Language Reference Manual [2] (LRM) pro- vides the semantics of the language in an informal prose form. Several formal models of VHDL semantics have been proposed which characterize VHDL semantics though some have only concentrated on a small subset of VHDL. Most approaches provide an operational or denotational definition of the LRM simulation cycle. Formal models have been demonstrated as being useful in proving the correctness of VHDL programs where a behavioral description of a circuit is shown to be equivalent to a structural description [3]. One disadvantage of the operational approaches is that they bind the meaning of a VHDL description to one particular method of executing its simulation. Therefore, alternative mechanisms of simulating VHDL (e.g., time warp synchronized parallel simulation [4]) cannot be validated against these models. This paper describes a model (referred to as the dynamic model) of the dynamic semantics of VHDL using interval temporal logic [5]. Essentially, the semantics of a VHDL description is defined in terms of sets of time intervals in which VHDL statements are evaluated and the values that signals and variables take on in these intervals. This effort aims to 1) define a comprehensive semantic model that characterizes most of the important features of VHDL, 2) capture the complex timing issues which are an integral part of the language, 3) define VHDL semantics in terms of the net effect of its evaluation rather than characterizing any particular method of simulation, and 4) demonstrate the utility of the model in validating rewrite rules and formally reasoning about the timing issues of VHDL. A significant advantage of this approach is that equivalences of VHDL programs can be established without resorting to a step-by-step simulation of the programs. One can look at a VHDL program and construct sets of time intervals that satisfy the axioms laid down in the dynamic model and infer the values of the signals at various time intervals in the simulation. Further, the dynamic model provides the ability to establish equivalence with respect to a specific set of signals in the VHDL program. It also provides the ability to observe only the stable waveforms of signals allowing one to ignore temporary transitions on signal values. Some of the features of VHDL are not characterized in this work. In particular, 1) issues related to configurations, generate statements and libraries are not addressed (these 1 Transformation rules may either be used by synthesis tools or serve to optimize performance of CAD tools such as simulators for VHDL. 2 These methods are useful for proving correctness of hardware designs where one VHDL description is a high-level requirements specification of the design and the other describes a low-level implementation of the same. 0278–0070/99$10.00  1999 IEEE