A VLSI neuromorphic device for implementing spike-based neural networks Giacomo INDIVERI a,1 and Elisabetta CHICCA a,b a Institute of Neuroinformatics, University of Zurich and ETH Zurich Winterthurerstrasse 190, Zurich, Switzerland b Cognitive Interaction Center of Excellence (CITEC), University of Bielefeld Universitätstrasse 21-23, Bielefeld, Germany Abstract. We present a neuromorphic VLSI device which comprises hybrid ana- log/digital circuits for implementing networks of spiking neurons. Each neuron in- tegrates input currents from a row of multiple analog synaptic circuit. The synapses integrate incoming spikes, and produce output currents which have temporal dy- namics analogous to those of biological post synaptic currents. The VLSI device can be used to implement real-time models of cortical networks, as well as real-time learning and classification tasks. We describe the chip architecture and the analog circuits used to implement the neurons and synapses. We describe the functionality of these circuits and present experimental results demonstrating the network level functionality. Keywords. Neuromorphic circuits, Integrate-and-Fire (I&F) neuron, synapse, Winner-Take-All (WTA), Address-Event Representation (AER), spike-based plasticity, STDP, learning Introduction With the technological advancements in both conventional computing architectures and custom Very Large Scale Integration (VLSI) implementations, spiking neural networks have been gaining renewed interest in recent years [9,16,20,28,29,34]. Hardware imple- mentations of spiking neural networks can be useful tools for basic research investiga- tions (e.g., by computational neuroscientists), and for exploring the implementation of alternative classes of brain-inspired general-purpose computational architectures. Exam- ples of devices recently proposed to build hardware networks of spiking neurons range from reconfigurable arrays of Integrate-and-Fire (I&F) neuron models [11,12,27,33], to learning architectures implementing detailed models of spike-based synaptic plastic- ity [2,3,10,26,27,36,39]. Within this context we propose a neuromorphic VLSI device that comprises an ar- ray of I&F silicon neurons and a matrix of synapse circuits that exhibit biologically real- istic synaptic dynamics and implement a spike-driven learning mechanism. The silicon 1 Corresponding Author; E-mail: giacomo@ini.phys.ethz.ch. Neural Nets WIRN11 B. Apolloni et al. (Eds.) IOS Press, 2011 © 2011 The authors and IOS Press. All rights reserved. doi:10.3233/978-1-60750-972-1-305 305