IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 54, NO. 5, MAY 2007 981 A Multichip Pulse-Based Neuromorphic Infrastructure and Its Application to a Model of Orientation Selectivity Elisabetta Chicca, Member, IEEE, Adrian M. Whatley, Patrick Lichtsteiner, Vittorio Dante, Tobias Delbruck, Senior Member, IEEE, Paolo Del Giudice, Rodney J. Douglas, and Giacomo Indiveri, Senior Member, IEEE Abstract—The growing interest in pulse-mode processing by neural networks is encouraging the development of hardware im- plementations of massively parallel networks of integrate-and-fire neurons distributed over multiple chips. Address-event represen- tation (AER) has long been considered a convenient transmission protocol for spike based neuromorphic devices. One missing, long-needed feature of AER-based systems is the ability to acquire data from complex neuromorphic systems and to stimulate them using suitable data. We have implemented a general-purpose solution in the form of a peripheral component interconnect (PCI) board (the PCI-AER board) supported by software. We describe the main characteristics of the PCI-AER board, and of the related supporting software. To show the functionality of the PCI-AER infrastructure we demonstrate a reconfigurable multichip neuro- morphic system for feature selectivity which models orientation tuning properties of cortical neurons. Index Terms—Address event representation (AER), asyn- chronous, cooperative–competitive, neural chips, neural networks, neuromorphic, orientation tuning, peripheral component inter- connect (PCI)-AER, VLSI, winner take all (WTA). I. INTRODUCTION N ETWORKS of integrate-and-fire (I&F) neurons have been shown to exhibit a wide range of useful compu- tational properties, including feature binding, segmentation, pattern recognition, onset detection, input prediction, etc. [1]. Implementing these functionality in VLSI circuits could lead to the construction of efficient hardware systems capable of solving complex sensory processing tasks in real-time. I&F neuron circuits are very well suited for VLSI implementation [2]–[8]. Large VLSI networks of I&F neurons can already be implemented on single chips, using today’s technology. However implementations of pulse-based neural networks on multichip systems offer greater computational power and higher Manuscript received November 22, 2005; revised June 29, 2006, October 9, 2006. This work was supported in part by the EU under Grant ALAVLSI IST-2001-38099, Grant CAVIAR IST-2001-34124, and Grant DAISY (FP6-2005-015803 and in part by the Swiss National Science Foundation unde Grant PMPD2-110298/1. This paper was recommended by Associate Editor G. Cauwenberghs. E. Chicca, A. M. Whatley, P. Lichtsteiner, T. Delbruck, R. J. Douglas, and G. Indiveri are with the Institute of Neuroinformatics (INI), University of Zurich, Zurich CH-8057, Switzerland and the Swiss Federal Institute of Technology (ETHZ), Zurich CH-8092, Switzerland. V. Dante is with the Italian National Institute of Health, 00161 Rome, Italy. P. Del Giudice is with the Italian National Institute of Health, 00161 Rome, Italy, and also with the National Institute of Nuclear Physics (INFN), 00185 Rome, Italy. Digital Object Identifier 10.1109/TCSI.2007.893509 flexibility than single-chip systems. As inter-chip connectivity is limited by the small number of input-output connections available with standard chip packaging technologies, it is necessary to adopt time-multiplexing schemes for constructing large multichip networks. A. Address Event Representation (AER) In recent years, we have witnessed the emergence of new asynchronous communication protocols that allow aVLSI neu- rons to transmit their activity across chips using pulse-frequency modulated signals (in the form of events, or spikes). One of the most common asynchronous communication protocols used in these types of systems is the so-called address-event represen- tation (AER) communication protocol [9]–[12]. In this repre- sentation, input and output signals are real-time digital events that carry analog information in their temporal relationships (inter-spike intervals). Each event is represented by a binary word encoding the address of the sending node. The activity of biological neurons is sparse in time, with typ- ical firing rates ranging from a few per second to a few hundred per second. The speed of digital buses (tens of megahertz) al- lows the outputs of many VLSI neurons firing at these biologi- cally typical rates to be multiplexed over one AE bus. To further reduce the bandwidth required on the AE bus, local connectivity can be hardwired on-chip [4], [8]. To handle cases in which mul- tiple sending nodes attempt to transmit their addresses at exactly the same time (event collisions) on-chip arbitration schemes can be used [9], [13]–[15]. Chips that communicate using the AER communication pro- tocol can be divided into senders with AER output only (e.g., silicon retinas [16], [17], or silicon cochleas [18]), receivers with AER input only [19], and transceiver chips, which are both senders and receivers [2], [7], [8]. Systems containing more than one AER sender chips can be assembled using off-chip arbitration. One of the earliest multichip systems using the AER commu- nication protocol, a silicon model of stereoscopic vision, was implemented by Misha Mahowald [9]. The system, consisting of three silicon chips interconnected with asynchronous digital buses, was able to extract, in real-time, depth information from visual stimuli detected by two silicon retinas. At that time and since, logic analyzers were and are often used to monitor AE buses. While still useful for debugging problems with AE pro- tocol communication they suffer from several disadvantages for 1549-8328/$25.00 © 2007 IEEE