IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 51,NO. 1, JANUARY 2004 83 Modeling of Thermal Behavior in SOI Structures Feixia Yu, Ming-C. Cheng, Member, IEEE, Peter Habitz, and Goodarz Ahmadi Abstract—Several physics-based analytical steady-state heat flow models for silicon-on-insulator (SOI) devices are presented, offering approaches at different levels of accuracy and efficiency for prediction of temperature profiles induced by power dissi- pated in SOI MOSFETs. The approaches are verified with the rigorous device simulation based on the energy transport model coupled with the heat flow equation. The models describe the one-dimensional temperature profile in the silicon film of SOI structure and two-dimensional heat flow in FOX, accounting for heat loss to the substrate via BOX and FOX, heat loss to (or gain from) interconnects, and heat exchanges between devices. These models are applied to investigate thermal behavior in single SOI devices and two-device SOI structures. Index Terms—Characteristic thermal length, self-heating, silicon-on-insulator (SOI), thermal resistance. I. INTRODUCTION S ILICON-ON-INSULATOR (SOI) has recently become a leading candidate for high-performance MOS ICs due to suppression of short-channel effects. However, because of the low thermal conductive BOX, heat generated in the SOI device cannot be efficiently dissipated to the substrate via BOX. This yields high device temperature and enhances heat flow to inter- connects, leading to higher interconnect temperature in SOI ICs. Self-heating has been extensively studied in recent years, and its significant influences on device/interconnect temperature, elec- trical characteristics and reliability have been observed [1]–[8]. Self-heating in SOI is usually taken into account using an ef- ficient single-temperature (ST) one-dimensional (1-D) thermal circuit [1], [9]–[11] implemented in BSIMSOI [11], where only 1-D heat flow from the channel to the substrate via BOX is con- sidered. Recent studies have revealed large variation in silicon- film temperature [6], [7], which can not be described by the constant temperature ST circuit. In this paper, three steady-state analytical SOI thermal models at different coarse-grained levels of description are presented. These models are able to account for 1-D heat flow in the silicon film and two-dimensional (2-D) heat loss to the substrate via BOX/FOX. Two-dimensional temperature profiles in FOX can be reasonably predicted, and heat loss to the interconnects and heat exchanges between devices are incorporated into the developed models. In this paper, thermal Manuscript received June 5, 2003; revised October 21, 2003. This work was supported in part by the New York State Office of Science, Technology, and Aca- demic Research, and by the National Science Foundation under Grant DMR- 0121146. The review of this paper was arranged by Editor J. Vasi. F. Yu and M.-C. Cheng are with the Department of Electrical and Computer Engineering, Clarkson University, Potsdam, NY 13699-5720 USA (e-mail: mcheng@clarkson.edu). P. Habitz is with IBM Microelectronics, Essex Junction, VT 05452 USA. G. Ahmadi is with the Department of Mechanical and Aeronautical Engi- neering, Clarkson University, Potsdam, NY 13699-5720 USA. Digital Object Identifier 10.1109/TED.2003.820939 Fig. 1. SOI device structure in the simulation. The dash lines divide the film into six regions, labeled by the numbers. and are the interface temperatures in the silicon film at and , respectively. is the lateral diffusion length, and . resistance in the silicon film is used to describe the heat loss to BOX/FOX instead of using SOI channel thermal resis- tance [4], [10], [12] (see Section III) in the conventional approaches. The developed models are verified with the Atlas 2-D-device simulator [13] including self-heating. Ultimately, the developed models will be able to do the following: 1) predict for more accurate SOI device modeling and reliability prediction; 2) model heat flow to interconnects more accurately for study of interconnect reliability; and 3) improve on the ST circuit for electrothermal circuit sim- ulation. II. SOI DEVICE STRUCTURES AND THERMAL PARAMETERS The SOI -channel MOSFET structure for this study is given in Fig. 1, where m, m, m, gate oxide thickness nm, source/drain metal contact length m, FOX length m, m, m, and silicon thin-film length m. Threshold voltages for the nMOS SOI devices with 40, 70, 150, and 400 nm are estimated to be 0.219, 0.225, 0.227, and 0.228 V, respectively. A simplified two-device SOI structure given in Fig. 2 is used to study heat exchange between devices. These two devices are identical to the single SOI devices. This SOI structure, al- though simple, provides a basic configuration for realistic heat exchange between the Device-I drain and Device-II source via the copper M1 line and FOX. For simplicity, the via and inter- connect cross sections are taken to be the same, m , where is the device width. Each interconnect length ( or ) includes total height of the vias and length of the M1 line. In simulation, via height is 0.5 m, and M1 line lengths are taken as m and m. Length and thickness of the poly line are chosen to be m and m. 0018-9383/04$20.00 © 2004 IEEE