1580 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATEDCIRCUITS AND SYSTEMS, VOL. 23, NO. 11, NOVEMBER 2004
VI. CONCLUSION
In this paper, we presented PILOT, an improved algorithm for
QR-compression-based fast iterative solver and apply it to parasitic
capacitance extraction problems modeled on surface-based method of
moments. The regular geometry decomposition scheme of FMM and
improved compression capability of are combined together to
yield an algorithm with superior efficiency. From the perspective,
the concept of rank-map and fine-tuning through merges and splits
is replaced by the a priori merged interaction list, enabled through
exploitation of the regular oct-tree structure in FMM. As a result, ac-
curate prediction of predetermined low epsilon-rank blocks is possible
and this, in turn, reduces the setup time of the process. Compared to
the FMM interaction list, greater compression is achieved through
merging source sibling cubes and observer cubes in their interaction
list to form the merged interaction list. The resultant blocks in the
list are then QR-compressed. The merged interaction list, like the
rank-map of is created only once for a given Green’s function.
However, due to the regular pattern of cubes, far fewer epsilon-rank
evaluations are required to construct the list compared to the original
binary-tree rank map.
The simulation results presented demonstrate the relative efficiency
of the PILOT algorithm compared to existing QR methods and
FastCap, in terms of setup time, memory, and matrix-vector products
for large number of excitations. While we have discussed PILOT only
in the context to parasitic capacitance extraction, continuing work
focuses on its application to full-wave kernels in multilayered media
for electrically small structures where classical FMM techniques break
down.
ACKNOWLEDGMENT
TheauthorsthankProf.M.Gu,DepartmentofMathematics,Univer-
sity of California, Berkeley, for stimulating discussions on this topic,
and the reviewers for their suggestions for improvement.
REFERENCES
[1] G. Servel and D. Deschacht, “On-chip crosstalk evaluation between ad-
jacentinterconnections,”in Proc. 7th IEEE Int. Conf. Electron., Circuits,
Syst., vol. 2, 2000, pp. 827–834.
[2] Y. Im and K. Roy, “A novel high-performance predictable circuit archi-
tecture for the deep submicron era,” in Proc. IEEE Custom Integrated
Circuits Conf., 2000, pp. 503–506.
[3] M. Kuhlmann, S. S. Sapatnekar, and K. K. Parhi, “Efficient crosstalk
estimation,” in Proc. Int. Conf. Comput. Design, 1999, pp. 266–272.
[4] E. A. Dengi and R. A. Rohrer, “On-chip interconnect modeling tech-
nologies,” in Proc. IEEE 6th Topical Meeting Elect. Perform. Electron.
Packag., 1997, p. 41.
[5] K. Kundert, H. Chang, D. Jefferies, G. Lamant, E. Malavasi, and F.
Sendig,“Designofmixed-signalsystems-on-a-chip,” IEEE Trans. Com-
puter-Aided Design, vol. 19, pp. 1561–1571, Dec. 2000.
[6] N. K. Verghese, T. J. Schmerbech, and D. J. Allstot, Simulation
Techniques and Solutions for Mixed-Signal Coupling in Integrated
Circuits. Norwell, MA: Kluwer, 1995, p. 160.
[7] A. Husain, “Models for interconnect capacitance extraction,” in Proc.
Int. Symp. Quality Electron. Design, 2001, pp. 167–172.
[8] R. F. Harrington, Field Computation by Moment Methods. NewYork:
IEEE Press, 1991.
[9] T.-Y. Chou and Z. J. Cendes, “Capacitance calculation of IC packages
using the finite element method and planes of symmetry,” IEEE Trans.
Computer-Aided Design, vol. 13, pp. 1159–1166, Sept. 1994.
[10] S. Kapur and D. E. Long, “ : efficient electrostatic and electromag-
netic solution,” IEEE Comput. Sci. Eng., vol. 5, pp. 60–67, Oct./Dec.
1998.
[11] S. Kapur and D. Long, “ : A fast integral equation solver for ef-
ficient 3-dimensional extraction,” in Proc. IEEE/ACM Int. Conf. Com-
puter-Aided Design, Nov. 1997, pp. 448–455.
[12] S.Kapur,D.Long,andJ.Zhao,“Efficientfullwavesimulationinlayered
lossy medium,” in Proc. IEEE Custom Integrated Circuits Conf., May
1998, pp. 211–214.
[13] K. Nabors and J. White, “FastCap: A multipole accelerated 3-D capac-
itance extraction program,” IEEE Trans. Computer-Aided Design, vol.
10, pp. 1447–1459, Nov. 1991.
[14] J. R. Phillips and J. White, “A precorrected-FFT method for electrostatic
analysis of complicated 3-D structures,” IEEE Trans. Computer-Aided
Design, vol. 16, pp. 1059–1072, Oct. 1997.
[15] H.A.vanderVorst,“Krylovsubspaceiteration,” Comput. Sci. Eng.,vol.
2, no. 1, pp. 32–37, 2000.
[16] G. H. Golub and C. F. Van Loan, Matrix Computations, 2nd ed. Balti-
more, MD: Johns Hopkins Univ. Press, 1989.
[17] A. Cangellaris and Y. Ling, “Rapid calculation of electrostatic green’s
functions in layered dielectrics,” IEEE Trans. Magn., vol. 37, pp.
3133–3136, Sept. 2001.
[18] R. J. Anderson, “Tree data-structures for N-body simulation,” SIAM J.
Comput., vol. 28, no. 6, pp. 1923–1940.
[19] A. E. Ruehli and P. A. Brennan, “Efficient capacitance calculations for
three-dimensional multiconductor systems,” IEEE Trans. Microwave
Theory Tech., vol. 29, pp. 76–82, Feb. 1973.
[20] D. Wilton, S. Rao, A. Glisson, D. Schaubert, O. Al-Bundak, and C.
Butler,“Potentialintegralsforuniformandlinearsourcedistributionson
polygonal and polyhedral domains,” IEEE Trans. Antennas Propagat.,
vol. 32, pp. 276–281, Mar. 1984.
Accurate and Efficient Modeling of SOI MOSFET With
Technology Independent Neural Networks
S. Hatami, M. Y. Azizi, H. R. Bahrami, D. Motavalizadeh, and
A. Afzali-Kusha
Abstract—This paper presents neural network (NN) approaches for mod-
eling the – characteristics of silicon-on-insulator MOSFETs. The mod-
eling approach is technology independent, fast, and accurate, which makes
it suitable for circuit simulators. In the model, two different NN architec-
tures, namely, multilayer perceptron and generalized radial basis function,
are used and compared. To increase the training efficiency of the NN, both
modular and region partitioning methods have been proposed and utilized.
In addition, two approaches for obtaining the transconductance and output
conductance of the device are discussed. The first approach makes use of an
NN for the conductances, while the second uses the numerical differentia-
tion of the - results. To confirm the accuracy of the model, the drain-cur-
rent characteristics as well as conductances obtained by the model are com-
pared to the simulation data for the points where the NNs are not trained.
The comparison shows excellent agreements with relative errors of around
1% over a wide range of drain and gate voltages as well as channel lengths
and widths.
Index Terms—Circuit simulation, fully depleted (FD), - character-
istic, neural network (NN) modeling, partially depleted (PD), silicon-on-in-
sulator (SOI) modeling, technology independent modeling, unified mod-
eling.
I. INTRODUCTION
MOSFET devices in silicon-on-insulator (SOI) technology have
many advantages over bulk counterparts, such as lower parasitic
capacitance and radiation hardness. The silicon layer on the oxide
Manuscript received March 18, 2003; revised December 19, 2003. This paper
was recommended by Associate Editor C.-J. R. Shi.
The authors are with the Department of Electrical and Computer Engi-
neering, Faculty of Engineering, University of Tehran, Tehran, Iran (e-mail:
hatami_safar@yahoo.com; y.azizi@ece.ut.ac.ir; hrbahrami@yahoo.com;
motavalizadeh@yahoo.com; afzali5@gmail.com).
Digital Object Identifier 10.1109/TCAD.2004.836725
0278-0070/04$20.00 © 2004 IEEE