Analytical Modelling of Communication in the Rectangular Mesh NoC M Moadeli 1 , A Shahrabi 2 , W Vanderbauwhede 1 1: Department of Computing Science University of Glasgow Glasgow, UK Email: {mahmoudm, wim}@dcs.gla.ac.uk 2 : School of Computing and Mathematical Sciences Glasgow Caledonian University Glasgow, UK Email: a.shahrabi@gcal.ac.uk Abstract Networks on chip (NoC) emerged as a packets switched, structured communication medium for development of the future systems on chip (SoC). Due to its unique features in terms of scalability and ease of synthesis, the (rect- angular) mesh topology is regarded as an appropriate candidate for on-chip network development. This paper presents an analytical model of the average message la- tency for rectangular mesh topology. The validity of the analysis is verified by comparing the model against the results produced by a discrete-event simulator. 1 Introduction Traditionally, interconnect architectures for integrated cir- cuits have been bus-based. Driven by the advances in semiconductor technologies reaching sub-0.1µm gate lengths, realization of the systems-on-chip (SoC) consist- ing of billions of gates and hundreds of processing units operating at different clock frequencies are becoming re- ality. As a bus is inherently non-scalable and at the same time the size and complexity of the future SoC does not allow starting the whole design from the scratch, em- ploying a modular type of SoC development seems in- evitable. Communication centric architectures or "net- works on chip" (NoC) have recently been proposed as a solution for the interconnect problem in large SoC designs [16]. The main driving factor behind employing NoC has been decoupling the communication fabric from the pro- cessing elements. NoCs help resolve the electrical prob- lems in new deep sub-micron technologies, as they allow to structure and manage global wires. At the same time the wires are used more efficiently, requiring fewer wires. A NoC architecture also leads to lower power consump- tion by implementing the concept of the GALS (glob- ally asynchronous, locally synchronous) on a chip and en- hances reliability [5]. Moreover, the NoC paradigm pro- vides the mechanism to develop and verify the IPs inde- pendently. As a result, NoCs have come to be regarded as the favored on-chip communication paradigm by offering a unified solution to a wide range of challenges in devel- opment of the large MPSoC [11]. The topology of an on-chip network specifies the structure in which routers connect the IPs together. A NoC may have any topologies proposed for interconnec- tion networks. Some of the architectures introduced or adopted for the NoC domain are fat tree [10], butterfly-fat tree [12], mesh [14], torus [16], folded torus [17] and vari- ations of the ring in octagon [1] and the Spidergon scheme [8]. 978-1-4244-1890-9/07/$25.00 ©2007 IEEE