Analysis of Transistor Networks Generation Leomar S. da Rosa Junior 1,2 , Felipe R. Schneider 3 , Renato P. Ribas 1,2 , André I. Reis 3 {leomarjr, felipers, rpribas}@inf.ufrgs.br , are@nangate.com 1 Nangate Research Lab – Instituto de Informática – Universidade Federal do Rio Grande do Sul, Brazil 2 Programa de Pós-Graduação em Microeletrônica – Universidade Federal do Rio Grande do Sul, Brazil 3 Nangate Inc. – Menlo Park, CA, USA ABSTRACT This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of CMOS logic gate networks. Different properties of transistor networks are used to explain features and limitations of previous methods. We describe which figures of merit, including the logical effort, affect the design quality of a cell transistor network. Further, we propose and compare two different approaches that generate transistor network with guaranteed theoretical minimum length transistor chains, showing it reduces significantly the logical effort of the networks. 1. INTRODUCTION VLSI design has firmly established a dominant role in the electronics industry. Automated tools have held designers to manipulate more transistors on a design project and shorten the design cycle. In particular, logic synthesis tools have contributed significantly to reduce the cycle time. In full-custom designs, manual generation of transistor netlists for each functional block is performed, but this is an extremely time-consuming task. In this sense, it becomes comfortable to have efficient algorithms to derive transistor networks automatically. Furthermore, some logic synthesis tools are extensively based on using Binary Decision Diagrams (BDDs) [1]. Classical BDDs based on Shannon’s decomposition naturally correspond to circuits built by Shannon’s decomposition algorithm. Therefore, not only BDDs can be used as compact and convenient representation of logic functions, but as a structure for direct synthesis of logic cells and circuits. Most methods for generation of transistor networks from BDDs use a non-disjoint pull-up/pull-down plane. This is the case of the methods presented in [2-7]. Some alternative methods presented in [8-11] derive disjoint planes: a pull-down composed of NMOS switches and a pull-up composed of PMOS switches. The drawback of these methods is the requirement of a special kind of BDDs with a serial/parallel structure. This way, the methods in [8-11] are not applicable to the widely used ROBDDs (Reduced and Ordered BDDs). The approaches in [12] and [13] use disjoint planes with ROBDDs, with subsequent simplifications. The simplifications performed by [12] are based on permissible functions, while the simplifications proposed in [13] are based on the unateness property of logic functions. In this paper, we describe two different methods for transistor network generation that respect the lower bound for the number of serial connected switches in a given logic cell. In addition, six kinds of CMOS network topologies are compared using some figures of merit, including the logical effort [14] for the cell. 2. BDDS AND TRANSISTOR NETWORKS There are several methods for deriving transistors networks from BDDs in the literature. Some of them are closely related to the use of multiplexer-based logic. These methods may require additional area because the number of necessary switches to implement a multiplexer is noticeably expensive. Other approaches use direct switches association to BDD arcs to build the logic cells. These solutions are more feasible since the total number of transistors required for the implementation can be drastically reduced if compared to multiplexer-based solution. In this context, the basic action when deriving a transistor network from a BDD is to associate a controlled switch to each arc of a BDD node. This concept is illustrated in Fig. 1, which shows a BDD node and four possible ways to associate transistor switches: CMOS pair, NMOS only, PMOS only and mixed PMOS/NMOS. BDD arcs connecting terminal nodes (0-terminal and 1-terminal) may be connected to VDD or GND. Usually, NMOS transistors are associated to BDD arcs leading to 0-terminal node, while PMOS transistors are associated to arcs leading to 1-terminal node. The main reason for this sort of association is to guarantee a good conduction from the power sources (VDD and GND) to the internal nodes. The exception occurs in the NPTL-like logic styles (NMOS Pass Transistor Logic), which are composed of NMOS transistors only. Fig. 2 illustrates this concept, where a NPTL network (Fig. 2.b) is derived from a BDD (Fig. 2.a). Drain inputs may be used to reduce the number of transistors in a cell derived from a BDD. When a node of a BDD represents a function corresponding to a single literal, like a or a , it is not necessary to use any switch to implement the node. The electrical node corresponding to the literal may be connected directly to the drains of the transistors corresponding to arcs in the BDD that point to the literal node. This is illustrated in Fig. 2.c, where the node C generates a drain input in the network. The drawback of drain inputs is that the fanin capacitance they add to the driving node is not constant. That means that the capacitance seen by the driving node is variable and depends on the values of other inputs controlling the transistor in a drain