1 DESIGN OPTIMIZATION OF CUSTOM ENGINEERED SILVER-NANOPARTICLE THERMAL INTERFACE MATERIALS Viral Chhasatia, Fan Zhou, Ying Sun ∗ , Liwei Huang, and Howard Wang State University of New York at Binghamton Mechanical Engineering Binghamton, NY 13902, USA ∗ Phone: (607)777-3881 Fax: (607)777-4620 Email: ysun@binghamton.edu ABSTRACT Thermal interface material (TIM) is a major hurdle in heat flow for typical chip/heat sink assemblies. In many electronic devices, hot spots occur in areas of high activity during the device operation. These hot spots can lead to high thermal gradients, which in turn result in performance and reliability hindrances. The elevated, non-uniform power density confronted with conventional TIMs that contain a uniform layer of high thermal conductivity material for the entire chip can be extremely insufficient in many applications. In this paper, a custom engineered, Ag-nanoparticle (Ag-NP) TIM that targets directly to the high power density region is introduced for achieving better thermal-mechanical-electrical performance at low cost. These nanoparticles can be inkjet printed on hot spots and sintered at a relative low temperature (~120°C) to create a continuous metallic layer that is in good contact with both the chip and heat sink, whereas the conventional particle-laden TIM covers the lower power density area. A computational model is developed to examine the overall thermal performance and reliability of the hybrid Ag-NP/conventional TIM as a function of the bondline thickness, applied pressure, deposition pattern, and surface roughness. The results show great improvements compared with a high-performance indium solder. KEY WORDS: Thermal interface materials, nanoparticles, hot spot, reliability, design optimization NOMENCLATURE A area, m 2 ar aspect ratio c fatigue ductility exponent d surface roughness, μm E Young’s modulus, GPa k thermal conductivity, W/(m⋅K) N f number of cycles to failure P pressure, Pa Q heat flux, W R thermal resistance, K/W T temperature, K Greek symbols α coefficient of thermal expansion, K -1 Δε p strain amplitude δ bondline thickness, μm ε strain f ε ′ fatigue ductility coefficient ε f true fracture ductility ν Poisson ratio Subscripts eff effective s surface 0 stress free stage 1. INTRODUCTION Power dissipation in electronic devices is projected to increase over the next five to ten years to the range of 150- 250 W/cm 2 for high performance applications [1]. In a typical chip heat sink assembly, the thermal interface material (TIM) is the major hurdle in heat flow. Despite 20+ years of intensive R&D, the in-situ thermal conductivities of thermal interface materials remain in the 1-4 W/m-K range based on heterogeneous mixtures of conducting solids in polymer matrices. In addition, the temperature distribution throughout an electronics device can be extremely non- uniform. Hot spots often occur in areas of high activity during device operation. These hot spots can lead to excessive stresses on the chip, and result in performance and reliability hindrances. Fig. 1. Temperature contour of air-cooled Intel Pentium 4 Northwood. 351K 347 343 339 335 331 327 978-1-4244-1701-8/08/$25.00 ©2008 IEEE 419