Fault Tolerant Error Coding and Detection using Reversible Gates Rekha K. James, Shahana T. K, K. Poulose Jacob Sreela Sasi Cochin University of Science and Technology Gannon University Kochi, Kerala, India Erie, PA, USA E-mail: {rekhajames, shahanatk, kpj}@cusat.ac.in sasi001@gannon.edu Abstract - In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, quantum computing and nanotechnology. Low power circuits implemented using reversible logic that provides single error correction – double error detection (SEC-DED) is proposed in this paper. The design is done using a new 4 x 4 reversible gate called ‘HCG’ for implementing hamming error coding and detection circuits. A parity preserving HCG (PPHCG) that preserves the input parity at the output bits is used for achieving fault tolerance for the hamming error coding and detection circuits.  Keywords: fault tolerance, reversible logic, hamming code, low power designs I. INTRODUCTION Error correcting codes are traditionally used to battle the corruption of transmitted data by channel noise. The encoded data, or code words, are sent through the channel and decoded at the receiving end. During decoding the errors are detected and corrected if the amount of error is within the allowed, correctable, range. This range depends on the extra information, parity bits, added during encoding. Single-error-correcting and double-error- detecting (SEC-DED) codes are generally used for this purpose. There are many ways to construct SEC-DED codes, and one of the most commonly used code is the Hamming Code. As power has become a first-order design consideration, researchers have begun looking at techniques to reduce power consumption in error coding and detection circuitry. Energy loss during computation is an important consideration in low power digital design. Landauer’s principle states that a heat equivalent to kT*ln2 is generated for every bit of information lost, where ‘k’ is the Boltzmann’s constant and ‘T’ is the temperature [1]. At room temperature T, though the amount of heat generated may be less it cannot be neglected for low power designs. The amount of energy dissipated in a system bears a direct relationship to the number of bits erased during computation. Bennett showed that energy dissipation would not occur if the computations were carried out using reversible circuits [2] since these circuits do not lose information. Neither feedback nor fan-out is allowed in reversible circuits. Classical logic gates such as AND, OR and XOR are not reversible. Hence, these gates dissipate heat and may reduce the life of the circuit. So, reversible logic is in demand in power aware circuits. In recent years, reversible logic has emerged as one of the most important approaches for power optimization with its application in low power CMOS, nanotechnology and quantum computing. One of the main constraints in reversible logic is to minimize the number of reversible gates used and number of unutilized outputs called “garbage” produced. Garbage output refers to the output that is not used for further computations. In other words, it is not used as a primary output or as an input to another gate. As the number of inputs and outputs are made equal there may be a number of garbage outputs produced in certain reversible implementations. In literature, there are a number of existing reversible gates such as Fredkin gate [3], Toffoli Gate [4], Feynman Gate [5], Feynman Double Gate [6] etc. In this paper, a new reversible 4 x 4 HC gate (HCG) is proposed for implementing hamming error coding and detection circuits. Parity checking is one of the oldest, as well as one of the most widely used methods for error detection in digital systems. Detection of faults generated in a circuit can be done by using parity-preserving reversible logic gates. The feasibility of the parity-preserving approach in the design of reversible logic circuits was demonstrated by B. Parhami [6] with examples of adder circuits. In this research, a modified HCG in which the parity of the outputs matches with that of the inputs is proposed. This can be used along with other parity preserving reversible logic gates to generate the parity preserved / fault tolerant hamming code. Parity preserving characteristic of such gates allows the detection of single fault generated in the circuit at the circuit’s primary outputs in reversible logic design. The organization of this paper is as follows: The necessary background on reversible logic gates used for the current implementation is discussed initially. Then ‘HC gate’ (HCG) is proposed, and (7, 4) Hamming code generator is implemented using this gate without any garbage outputs. The design is chosen in such a way to reduce the number of gates, number of levels (delay) and number of garbage outputs to a minimum. A fault detection method for hamming code generator circuit based on parity-preserving reversible logic gates is introduced. The fault tolerant reversible hamming code generator implemented using such gates allow detection of single fault caused in the circuit. The design is then extended for the implementation of Hamming code error detector. Finally, a comparison in terms of number of reversible gates, garbage outputs and number of levels (delay) is done for all types of implementations.