Testing SerDes Beyond 4 Gbps – Changing Priorities Stephen Sunter & Aubin Roy LogicVision (Canada) Inc., Ottawa, Ont. K1Z 8R9 Abstract – After briefly reviewing conventional jitter and jitter tolerance tests for SerDes, this paper shows that ISI is a dominant source of bit errors above 4 Gbps, and is inadequately tested. We demonstrate the correlation between ISI and transition-density dependent delay (TDDD) at 3.1 Gbps, and provide detailed 6.25 Gbps silicon results for an undersampling digital BIST that can measure jitter, TDDD, and other parameters at production speeds with picosecond resolution. I. INTRODUCTION Bit error rate (BER) for a serializer/deserializer (SerDes) system can be predicted by measuring and summing (or convolving) different components of the transmitted jitter, and by measuring receiver jitter tolerance of different frequencies of sine-wave phase modulation. The total jitter (TJ) in high- speed data signals has the following constituent types of jitter: 1. Random jitter (RJ) 2. Deterministic jitter (DJ) 2 a Periodic jitter (PJ) 2 b Bounded uncorrelated jitter (BUJ) 2 c Data dependent jitter (DDJ) 2 c i Duty cycle distortion (DCD) 2 c ii Inter-symbol interference (ISI) For the transmitted signal, ever finer distinctions are being measured between TJ, RJ, and DJ since these values are specified in datacom standards such as SATA, PCI Express, and Fibre Channel. TJ for a transmitter is limited to typically one third of the unit interval (UI), so that the wire channel and the receiver can each contribute this much too. DJ and RJ are permitted to each comprise about half this. Thus, RJ is limited to less than 0.01~0.02 UI rms, since its rms value is multiplied by 14 to obtain its peak-to-peak value for 10 12 bits. As speeds have increased, RJ, PJ, BUJ, and DCD have scaled with the UI due to improvements in transmitter design. Testing for these types of jitter is still necessary, however, because a process or design technique can only improve jitter performance if the associated circuitry is free of manufacturing defects. Some SerDes manufacturers consider RJ as the most important jitter to test because its value is independent of most settings, it cannot be reduced by algorithmic means, the rms value is multiplied by 14 to predict TJ, and it is sensitive to process quality. Unfortunately, its near-picosecond rms value is the most difficult to measure accurately in a production test. The last jitter type listed, ISI, is caused by signal reflections due to impedance mismatches/discontinuities in the signal path and by the limited bandwidth of the transmission medium relative to the transmitter’s output signal. The cheapest medium for short distances is printed and twisted pair wiring, and it has a much lower bandwidth than multi-gigabit per second (Gbps) signals. Pre-emphasis and equalization are the primary design techniques for improving ISI. The frequency response for a backplane path between two boards can decrease at 20 dB per decade starting from below 200 MHz, so that the loss exceeds 30 dB at 6 GHz [1]. ISI in this case will be dominated by transition density dependent delay (TDDD): the phase delay for the signal is dependent on the density of bit transitions in the signal. Alternatively stated, the time for a signal to transition from one logic level to another depends on the voltage that it started from, which depends on how many same-value logic values preceded it, as can be seen in Fig. 1. Jitter tolerance is the ability of a receiver to tolerate low frequency (LF) jitter by tracking it well enough that only excess high frequency (HF) jitter causes bit errors. The tracking ability is permitted to decrease as the jitter frequency increases, up to some frequency, typically the data rate divided by 1667, as shown in Fig. 2. The ideal response is that of a “golden PLL” having a low-pass loop-filter corner frequency at f BAUD /1667. When measuring jitter, especially RJ, it is important to high-pass filter the jitter with a LF cut-off at f BAUD /1667. Triggering an oscilloscope with the transmitter’s reference clock seems to be a popular shortcut, despite its being specifically warned against in the MJSQ [2]. In [1] the authors measured 1.5 ps rms with 1 MHz as the LF cut-off versus only 0.64 ps rms with cut-off at f BAUD /1667 = 5 MHz. Clearly this difference would affect yield in a production test. Fig. 1. Zero-crossing point depends on the preceding bit values Fig. 2. Typical jitter tolerance mask f D /1667 (3.1 GHz/1667 = 1.8 MHz) 0.1 UI 1.5 UI Applied sinusoidal p-p jitter f D /25000 - 20 dB/decade BER <10 –12 135 IEEE 2007 Custom Intergrated Circuits Conference (CICC) 1-4244-1623-X/07/$25.00 ©2007 IEEE 9-1-1