538 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 53, NO. 3, MARCH 2006 Low-Frequency Noise in TaSiN/HfO nMOSFETs and the Effect of Stress-Relieved Preoxide Interfacial Layer Siva Prasad Devireddy, Student Member, IEEE, Bigang Min, Student Member, IEEE, Zeynep Çelik-Butler, Senior Member, IEEE, Hsing-Huang Tseng, Senior Member, IEEE, Philip J. Tobin, Member, IEEE, Fang Wang, Member, IEEE, and Ania Zlotnicka Abstract—Low-frequency noise characteristics are reported for TaSiN-gated n-channel MOSFETs with atomic-layer deposited HfO on thermal SiO with stress-relieved preoxide (SRPO) pretreatment. For comparison, control devices were also included with chemical SiO resulting from standard Radio Corporation of America clean process. The normalized noise spectral density values for these devices are found to be lower when compared to reference poly Si gate stack with similar HfO dielectric. Conse- quently, a lower oxide trap density of cm eV is extracted compared to over 3 cm eV values reported for poly Si devices indicating an improvement in the high- and interfacial layer quality. In fact, this represents the lowest trap density values reported to date on HfO MOSFETs. The peak electron mobility measured on the SRPO devices is over 330 cm V s, much higher than those for equivalent poly Si or metal gate stacks. In addition, the devices with SRPO SiO are found to exhibit at least higher effective mobility than RCA devices, notwithstanding the differences in the high- and inter- facial layer thicknesses. The lower Coulomb scattering coefficient obtained from the noise data for the SRPO devices imply that channel carriers are better screened due to the presence of SRPO SiO , which, in part, contributes to the mobility improvement. Index Terms— noise, flicker noise, hafnium oxide (HfO ), high- dielectrics, interfacial layer, low-frequency noise, metal gates, MOSFET, stress-relieved preoxide (SRPO), TaSiN. I. INTRODUCTION F UTURE miniaturization of MOSFETs would require high- dielectrics, with HfO leading the short list of possible candidates in terms of stability, CMOS compatibility and overall dielectric performance. Much effort is underway to incorporate dual metal gates in the process flow to overcome problems intrinsic to conventional polysilicon gates such as dopant diffusion, Fermi-level pinning due to the reactions Manuscript received July 29, 2005; revised November 17, 2005. This work was supported in part by Texas Higher Education Coordinating Board Advanced Technology Program under Grant 003656-0001-2001 and in part by Semicon- ductor Research Corporation under Contract 2004-VJ-1193. The review of this paper was arranged by Editor M. J. Deen. S. P. Devireddy and B. Min are with the Department of Electrical Engineering, University of Texas at Arlington, Arlington, TX 76019 USA. Z. Çelik-Butler is with the Nanotechnology Research and Teaching Fa- cility, University of Texas at Arlington, Arlington, TX 76019 USA (e-mail: zbutler@uta.edu). H.-H. Tseng and P. J. Tobin are with Freescale Semiconductor Inc., Austin, TX 78721 USA. F. Wang and A. Zlotnicka are with Freescale Semiconductor Inc., Tempe, AZ 85284 USA. Digital Object Identifier 10.1109/TED.2005.863769 at the junction with high- and depletion effects. Promising results have been reported as regards to integration and device characteristics with TaSiN and TiN gates on HfO [1]–[8]. Formation of some sort of interfacial layer is mostly un- avoidable and can be desirable as a transition from high- to the substrate [9], [10] in spite of the lowering effect on the overall dielectric constant. The thickness and properties of such a layer depend on high- deposition method, predeposition surface cleaning and/or post-deposition annealing conditions [11]. Recently, stress relieved thermal SiO interfacial layer formed by a new SRPO pretreatment method was shown to improve the short channel device characteristics [12]. However, its impact on the trap characteristics in HfO and the dielectric quality as a whole has not been studied. Low-frequency noise serves as a diagnostic tool with regards to the quality of the dielectric and the dielectric/Si interface as well as interface generated mobility degradation [13]–[17], which high- dielectrics are known to suffer from. However, it should be noted that mobility degradation in high- de- vices has also been attributed to remote phonon scattering [18]–[20]. The low frequency noise characteristics of MOS- FETs with TaSiN/HfO atomic-layer deposition (ALD)/SiO stress-relieved preoxide (SRPO) pretreatment and TaSiN/HfO (ALD)/SiO Radio Corporation of America (RCA) preclean gate stacks are reported here. The peak mobility for SRPO devices is greater than 330 cm V s and is about twice that reported for comparable poly Si/ HfO gate stacks. II. DEVICES AND MEASUREMENTS Three lot-splits were fabricated for this study with the same high- but varying interfacial layer thickness and interfacial oxide deposition method. Splits 1 and 2 had 6 and 10 Å of thermal SiO , respectively, formed by SPRO treatment beneath the 27-Å HfO layer. A 10-Å-thick chemical SiO resulting from standard RCA process formed the interfacial layer in Split 3, with 27 Å of HfO on top. In all splits, TaSiN was the gate electrode (work function eV) and the HfO layer ( ) was deposited by ALD. The poly Si gated device, which we call a reference device here, had 55 Å of HfO deposited by metal–organic chemical vapor deposition (MOCVD) with a chemical SiO interfacial layer [21]. All SiO thick- nesses are targeted values. 0018-9383/$20.00 © 2006 IEEE