A novel approach to reduce power consumption in level shifter for Multiple Dynamic Supply Voltage Marco Terres, Cristina Meinhardt, Guilherme Bontorin, Ricardo Reis Instituto de Informática, PGMICRO/PPGC UFRGS – Universidade Federal do Rio Grande do Sul Porto Alegre - Brazil {masmterres, cmeinhardt, gbontorin, reis}@inf.ufrgs.br Abstract— Multiple Dynamic Supply Voltage (MDSV) is an attractive way to reduce dynamic power in Integrated Circuits. This technique introduces Level Shifter (LS) in order to commute from one voltage domain to another. Nevertheless, some LS inserted during the physical synthesis can degrade performance and power consumption, especially in specific power modes. In this work, we present a novel approach to dynamically turn off idle LS, using an alternative path to current flows, according to the power mode of the regions that the nets are connected. The main advantages of this technique are when the nets connect regions with the same power mode. In this cases, this technique permits to save more than 35% power consumption and reduce the delay on 30% for NAND2 circuits. Keywords—Multiple Dynamic Supply Voltage (MDSV); Level Shifter; Power consumption, Physical Synthesis. I. INTRODUCTION The continuous shrink of MOS (Metal Oxide Semiconductor) technology allows incorporating more functions in a small area of silicon. This improvement is most visible in current portable devices. However, other than size constrains, these devices introduce demands for long life batteries for energy supply, on-chip thermal evacuation, and reliability problems [1]. Chandrakasan showed that the power consumption could be separated in three factors [2]: static power consumption, short circuit power and capacitive power. The static power consumption is due to leakage current through the MOS transistor. The short circuit power consumption occurs when the power supply (VDD) and the ground (GND) are directly connected. For example, in the complementary metal-oxide- semiconductor (CMOS) inverter, the short circuit current occurs when the PMOS and NMOS transistors are both in the conducting mode. Finally, the charging and discharging of load and parasitic capacitances produce the capacitive power consumption, which [2] call dynamical consumption. In CMOS circuits, the capacitive power consumption is proportional to the square of VDD. So, reducing VDD level, the global power consumption decrease. The penalty of this technique is degradation on circuit performance. Multi supply voltage circuits are an attractive method to decrease the power consumption locally in the circuit. Cells along critical paths are assigned to higher VDDs in order to assure high performance, while others are assigned to lower supply levels to save energy. The use of different values of voltage introduces some modifications on the normal standard cell synthesis flow. The most important change is the inclusion of Level Shifter (LS) between cells with different voltage source. The LS module is essential to allow cells from low voltage operation clusters to be connected to cells in high voltage operation. The insertion of LS influences the physical synthesis procedure creating the need of modifications in their algorithms. Moreover, as a contralateral effect, the LS insertion impacts the performance and power consumption of the circuits [3]. Two relevant algorithms to assign the voltage supply to gates in circuits with multi power supplies are: Clustered Voltage Scaling (CVS) [4] [5] and Extended Clustered Voltage Scaling (ECVS) [6]. An extension of CVS idea is Multiple Dynamic Supply Voltage (MDSV). This technique has been introduced [7] and supplies the clusters with different voltages levels, depending on the power mode selected. The main contribution of MDSV technique is the concept of dynamic voltage, i.e. the voltage level to supply the clusters can be changed during the circuit operation. Moreover, MDSV turn off temporally some unused clusters to further power savings. In this context, we present an alternative solution to deal with LS insertion in MDSV circuits. As the cluster voltages can be changed dynamically, some of LS inserted during the physical synthesis are idle in some operations mode. Thus, we turn dynamically those idle LS off. For this, we create an alternative path to current flows. Results show 38 % power save and a 30% reduction on delay. This paper is organized as following: Section II introduces the background of MDSV, Section III presents details on our approach, Section IV presents simulation results to finally conclude the paper on section V. 978-1-4799-2452-3/13/$31.00 ©2013 IEEE 715