IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 51, NO. 6, DECEMBER 2004 3767 Total Dose Effects on Double Gate Fully Depleted SOI MOSFETs Bongim Jun, Member, IEEE, Hao D. Xiong, Student Member, IEEE, Andrew L. Sternberg, Student Member, IEEE, Claude R. Cirba, Dakai Chen, Ronald D. Schrimpf, Fellow, IEEE, Daniel M. Fleetwood, Fellow, IEEE, James R. Schwank, Fellow, IEEE, and Sorin Cristoloveanu, Fellow, IEEE Abstract—Total ionizing dose effects on fully-depleted (FD) sil- icon-on-insulator (SOI) transistors are studied when the devices are operated in single gate (SG) and double gate (DG) mode. The devices exhibit superiority in mobility and drain current when op- erated in DG mode compared to SG mode. Moreover, the dc char- acteristics of DG operated device are less vulnerable to total dose radiation induced damage. In particular, radiation-induced inter- face traps have less electrical effect in DG mode operation. Index Terms—Charge coupling, double gate, fully-depleted (FD) silicon-on-insulator (SOI) transistors, total dose effects. I. INTRODUCTION R APIDLY developing silicon-on-insulator (SOI) tech- nology presents numerous advantages in terms of electrical performance, such as high speed and low power con- sumption when compared to traditional bulk silicon metal oxide semiconductor field effect transistors (MOSFETs) [1], [2]. In particular, double gate (DG)-mode SOI transistors can exhibit exceptional electrical performance, including higher drain current, effective mobility, transconductance and enhanced subthreshold swing due to charge coupling for reasonably thick Si-bodies and due to volume inversion in ultra thin Si-bodies [3]–[8]. These enhanced features are very appealing to space application designers. However, SOI devices are susceptible to total ionizing dose-induced charges that can be trapped in the buried oxide layer (BOX). Trapped positive charges may invert the back channel and create a leakage path at the island/BOX interface that severely degrades performance [9], [10]. In this paper, we investigate the relative radiation hardness of fully depleted (FD) SOI n-MOSFETs when operated in SG and DG modes. We have irradiated fully-depleted SOI devices with 10 keV x-rays and performed – measurements to assess the radiation-induced degradation. Moreover, we solve the Poisson-Density Gradient-Continuity [11]–[13] system of Manuscript received June 1, 2004; revised September 23, 2004. This work was supported by the Defense Threat Reduction Agency and AFOSR through the MURI Program, Sandia National Laboratories, and the U. S. Department of Energy’s National Nuclear Security Administration under Contract DE-AC04- 94AL85000. B. Jun, H. D. Xiong, A. L. Sternberg, C. R. Cirba, D. Chen, R. D. Schrimpf, and D. M. Fleetwood are with Vanderbilt University, Nashville, TN 37232 USA (e-mail: bongim.jun@vanderbilt.edu; hao.xiong@vander- bilt.edu; andrew.l.sternberg@vanderbilt.edu; claude.r.cirba@vanderbilt.edu; dakai.chen@vanderbilt.edu; ron.schrimpf@vanderbilt.edu). James R. Schwank is with the Sandia National Laboratories, Albuquerque, NM 87185 USA (e-mail: schwanjr@sandia.gov). S. Cristoloveanu is with the ENSERG, Grenoble Cedex 1 38016, France (e-mail: sorin@enserg.fr). Digital Object Identifier 10.1109/TNS.2004.839256 Fig. 1. Schematic cross-sectional diagram of a FD SOI MOSFET. The lightly doped drain (LDD) is not shown in the diagram. equations in order to evaluate the spatial and energy distribu- tions of electrons in the n-channel devices. The simulations illustrate the effects of increases in interface trap density and oxide charges for single and double gate operated FD SOI transistors. II. TRANSISTOR FABRICATION DETAILS Two types of NMOS transistors were used for this study; 1) devices fabricated on Ibis Advantox-170 SIMOX wafers and 2) devices fabricated on UNIBOND SOI wafers. Transistors on SIMOX wafers were fabricated at Sandia National Laboratories. A schematic diagram of a FD SOI transistor is shown in Fig. 1. The NMOS transistors fabricated on the SIMOX wafers were formed in a p-doped Si-film ( cm and nm). The top thin gate oxide thickness was nm and the thick buried oxide (BOX) was nm. The corresponding UNIBOND device parameters are: cm , nm, nm, and nm. The source and drain doping was cm and the substrate was p-doped with cm , respectively for both SIMOX and UNIBOND devices. III. SINGLE GATE AND DOUBLE GATE OPERATION A. Single Gate Mode For a fully depleted transistor with a thin Si-body, the single gate characteristics are strongly dependent on the opposite gate potential. Fig. 2(a) and (b) show the front and back channel char- acteristics, respectively, of an n-channel FD transistor with gate length and width of 10 m and 0.8 m. The drain currents are plotted with dotted lines while the corresponding transconduc- tance characteristics are plotted with solid lines. In Fig. 2(a), when the back interface is depleted, the threshold voltage grad- ually decreases and the transconductance peak increases and 0018-9499/04$20.00 © 2004 IEEE