BTI and HCI first-order aging estimation for early use in standard cell technology mapping P.F. Butzen a,⇑ , V. Dal Bem b , A.I. Reis b , R.P. Ribas b a Center for Computational Science, Federal University of Rio Grande, Rio Grande, Brazil b Institute of Informatics, Federal University of Rio Grande do Sul, Porto Alegre, Brazil article info Article history: Received 24 May 2013 Received in revised form 24 June 2013 Accepted 20 July 2013 abstract The performance degradation in digital integrated circuit (IC) caused by BTI and HCI aging effects has increased significantly at each new technology node, as well as their importance in terms of circuit reli- ability throughout the entire circuit lifetime. This work proposes an aging design cost estimation method to be exploited in standard cell IC design flow. This method must be simple and fast, although not so accurate, to be suitable for the intense interactive process during the technology mapping in the logic synthesis phase. The proposed aging cost has been verified and validated through SPICE simulations car- ried out over a large number of CMOS gates. Ó 2013 Elsevier Ltd. All rights reserved. 1. Introduction The transistor dimension scaling is the main artifice used by the semiconductor industry to increase the performance of integrated circuits (ICs). However, in the last decades, the continuous scaling down has evidenced several aspects ignored in earlier technology nodes. The circuit reliability has been pointed out as one of the ma- jor challenges in nanometer CMOS circuit design [1]. Indeed, aging mechanisms have become a critical issue to guarantee such reli- ability during the entire system lifetime. Among several aging mechanisms, hot carrier injection (HCI) and bias temperature instability (BTI) are of special interest since they cause severe cir- cuit performance degradation in the most advanced technologies, according to [2]. The great majority of ICs are designed based on the standard cell methodology. In this methodology, the design constraints have been traditionally focused on speed, dynamic power dissipation and area overhead. Recently, static power consumption and vari- ability have been incorporated in the IC design flow. Such informa- tion is being added in cell library data, whereas the algorithms for logic synthesis are being adapted to do a better exploitation of such aspects. Simpler reliability estimation metrics would allow reli- ability aspects to be considered during the first design steps. Many solutions to deal with aging degradation in different abstraction levels of IC design have been proposed in the literature [3–9]. At circuit level, some techniques insert additional modules to deal with performance degradation adapting supply and thresh- old voltages [3,4]. Other approaches explore the input signal dependence by reordering the gate inputs to mitigate the aging degradation [5–7]. The design flow and related algorithms have been treated in other approaches. However, only simple gates have been used in the aging evaluation [7] or the adopted standard cell libraries require previous and complete characterization [11]. At gate level, there are techniques that add a time slack margin to compensate the degradation by upsizing the transistors width [8], whereas other methods focus on the intrinsic robustness of transistor network arrangement [9]. The choice of CMOS gates de- signed in single and multiple stages is also investigated in [10]. Despite of those design solutions, there is still an important gap in the IC design flow in terms of reliability, which has been actually ignored in the circuit synthesis process. The most appropriate choice of the set of logic gates that compose the circuit may reduce significantly the effort spent in the subsequent stages. In this context, a reliability cost for CMOS gates can become a powerful design metric to be explored by the synthesis algorithms. One can- didate for such design cost is the average gate delay degradation due to aging effects. Such degradation is strongly influenced by the transistor arrangements and by the number of stages in logic gates, as discussed in [10]. However, the method presented in [10] to obtain this information for each logic gate is quite expen- sive as a large number of SPICE simulations is required. The main contribution of this paper is a simple and fast method to estimate the cost of CMOS gates, in terms of the impact in the circuit performance degradation due to BTI and HCI aging effects. For that, the method needs to be just accurate enough to support the choice of the most appropriate library cell during the technol- ogy mapping process, leading to the generation of a more robust circuit against aging degradation. This figure-of-merit can be also exploited for a first evaluation of the expected IC performance degradation without requiring time consuming electrical simulations. 0026-2714/$ - see front matter Ó 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2013.07.087 ⇑ Corresponding author. Tel.: +55 (53) 32336807; fax: +55 (53) 32336652. E-mail address: paulobutzen@furg.br (P.F. Butzen). Microelectronics Reliability 53 (2013) 1360–1364 Contents lists available at ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel