Energy Efficient Address Assignment Through Minimized Memory Row Switching Sambuddhi Hettiaratchi, Peter Y.K. Cheung, Thomas J.W.Clarke Department of Electrical and Electronic Engineering Imperial College of Science, Technology and Medicine, London Exhibition Road, London SW7 2BT, United Kingdom s.hetti@ic.ac.uk, p.cheung@ic.ac.uk, t.clarke@ic.ac.uk ABSTRACT Data transfer intensive applications consume a significant amount of energy in memory access. The selection of a memory location from a memory array involves driving row and column select lines. A signal transition on a row select line often consumes significantly more energy than a transition on a column select line. In order to exploit this difference in energy consumption of row and column select lines, we propose a novel address assignment methodology that aims to minimize high energy row transitions by assigning spa- tially and temporally local data items to the same row. The prob- lem of energy efficient address assignment has been formulated as a multi-way graph partitioning problem and solved with a heuristic. Our experiments demonstrate that our methodology achieves row transition counts very close to the optimum and that the method- ology can, for some examples, reduce row transition count by 40- 70% over row major mapping. Moreover, we also demonstrate that our methodology is capable of handling access sequences with over 15 million accesses in moderate time. Categories and Subject Descriptors B.5.1 [Register-Transfer-Level Implementation]: Design—Mem- ory design; B.5.2 [Register-Transfer-Level Implementation]: De- sign Aids—Automatic synthesis; Optimization General Terms Algorithms, Design, Experimentation, Performance Keywords address assignment, data layout, memory synthesis 1. INTRODUCTION In data transfer intensive applications, such as video and image processing, a significant fraction of the total energy consumption of the system is due to memory access [16]. Dynamic power dis- sipation is significant in CMOS circuits, and therefore, behavioural Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. ICCAD ’02 San Jose, California, USA Copyright 2001 ACM X-XXXXX-XX-X/XX/XX ...$5.00. level energy minimization efforts often attempt to minimize signal transition counts, particularly on high capacitance nodes [13]. In order to minimize switching activity caused by memory ac- cess, it is necessary to have some knowledge about the access se- quences. For many application-specific integrated circuits (ASICs), the access sequences are usually known a priori. ASICs may also contain data dependent access sequences. However, because the application is known, statistical information can be collected about the data dependent sequences. Information about the access se- quences enable the application of energy optimizations to ASICs which would not be applicable to general purpose systems. CMOS memory cell arrays are usually organized into rectangu- lar blocks of memory cells. The selection of a memory location involves driving row, column and in some cases block select sig- nals. Signal transitions on high capacitance signals such as the row and block select lines consume more energy compared to those on column select lines [3]. In this paper, we present a methodology for minimizing the en- ergy consumption of memory access through address assignment that minimizes row switching. The novel contributions of this pa- per are: (1) formulation of the energy efficient address assignment problem as a multi-way graph partitioning problem; (2) application of an existing graph partitioning heuristic to solve the problem; (3) evaluation of the solution in terms of quality of the solution and run time. This paper is organized as follows. Section 2 presents some of the previous work in the area of memory access energy minimiza- tion. Section 3 formulates the energy efficient address assignment problem as a graph partitioning problem. Section 4 contains a list of assumptions we have made in this work. Section 5 describes our address assignment methodology. Section 6 reports experimental results and Section 7 contains conclusions and indicates some pos- sible future work. 2. PREVIOUS WORK The relevant previous work of interest address the problem of reducing memory access energy in ASICs at the behavioural level. In-place mapping attempts to reduce required memory size by sharing physical memory locations amongst signals whose life- times do not overlap [15]. Smaller memories consume less energy per access compared to larger memories [2]. Therefore, memory size minimization techniques such as in-place mapping and loop transformations [16] usually reduce energy consumption. Minimiz- ing the number of memory accesses through loop transformations and packing several data items into a single memory word [14] also result in lower energy consumption. Most modern memory architectures are based on memory hier- ICCAD 2002, San Jose