PERGAMON MicroelectronicsReliability 39 (1999) 885-889 MICROELECTRONICS RELIABILITY www.elsevier.com/locate/microrel Leakage current variation during two different modes of electrical stressing in undoped hydrogenated n-channel polysilicon thin film transistors (TFTs) F.V.Farmakis a, J.Brini a, G.Kamarinos a, C.A.Dimitriadis b , V.K.Gueorguiev c and Tz.E.Ivanov c a LPCS, ENSERG, 23 rue des Martyrs, BP 257, 38016 Grenoble Cedex 1, France b Department of Physics, University of Thessaloniki, 54006 Thessaloniki, Greece c Institute of Solid States Physics, Bulgarian Academy of Sciences, 72 Tzarigradsko shaussee, 1784 Sofia, Bulgaria Abstract Leakage current evolution during two different modes of electrical stressing in hydrogenated-undoped n-channel polysilicon thin film transistors (TFTs) is studied m this work. On-state bias stress (high drain bias and positive gate bias) and off-state bias stress (high drain bias and negative gate bias) were performed in order to study the degradation of the leakage current. It is found that during off-state bias stress the gate oxide is more severely damaged than the SiO2-polySi interface. In contrast, during on-state bias stress, two different degradation mechanisms were detected which are analyzed. © 1999 Elsevier Science Ltd. All rights reserved. 1. Introduction Polycrystalline silicon thin film transistors (polysilicon TFTs) present a great interest as switching devices in active matrix liquid crystal displays (AMLCDs). For such applications, the leakage current Ire ~ plays a very important role. Therefore, the evolution of leakage current during different bias stress conditions has to be extensively studied. It has already been the subject of several works [1,2,3,4] especially during on- and off-state bias stress (for high drain voltage V D and positive and negative gate voltage VG). During on-state bias stress, it has been reported [3,4] interface states generation (acceptor-like) accompanied with hot- hole injection into the gate oxide. As far as off-state bias stress is concerned, Krishnan et al [5] proposed recently an interface states generation mechanism (donor-like states) which is masked from the transfer characteristics in the on-state regime. In this work, first we used light emission measurements to determinate the gate voltage (for a fixed high dram voltage) at which maximum ionization phenomena occur in the device. Then we applied two modes of stress: on-state bias stress (on- stressing) and off-state bias stress (off-stressing). The latter is obtained by applying a high V D and a negative Va. The aim of our study is to identify the degradation mechanisms of the polysilicon TFTs with application of both stress modes and to observe the evolution of the leakage current. We conclude that the evolution of the leakage current can be a reliable tool m order to study hot carrier effects m polysilicon TFTs. 0026-2714/99/$ - see front matter. © 1999 Elsevier ScienceLtd. All rights reserved. PII: S0026-2714(99)00118-3