QUALITY AND RELIABILITY ENGINEERING INTERNATIONAL, VOL. 11, 227-232 zyxwv (1995) zyxwv ~ Process/Equipment zyxwvutsrq Modifications CRITICAL AREA ANALYSIS FOR DESIGN-BASED YIELD IMPROVEMENT OF VLSI CIRCUITS DORIS SCHMIIT-LANDSIEDEL' , DORIS KEITEL-SCHULZ', JITENDRA KHARE3, SUSANNE GRIEP' AND WOJCIECH MALY3 zyxwvutsr 'Corporate Research and Development; ZSemiconductor Division, Siemens A G zyxwv 81 730 Munchen, Germany; and 3Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh PA 15225, U.S.A. Layout zyxwvutsr I 1 ' Yield Design Estimation Modifica bons SUMMARY V Yield improvements can be achieved by both contamination control (manufacturing) and defect sensitivity decrease (design). In this paper, the need for critical area analysis is demonstrated for design based yield prediction and improvement. Experimental results for a typical CMOS process are provided. V KEY WORDS: yield learning; critical area; design-based yield improvement; defect simulation; failure analysis 1. INTRODUCTION In modern IC manufacturing with its increasing com- petition, short time-to-profit is of prime importance. This requires, among other things, that the cost of manufacturing per working product be as low as possible. This cost is determined by die area and yield. Through tightening of the structure sizes the area decreases, but the yield may decrease as well. Thus, for cost efficient product planning the yield of a product and its dependence on structure sue must be known as precisely as possible. Increase of the production yield can be achieved by improved process and contamination control. This implies high efforts in installation of better equipment, in-situ monitoring techniques, failure analysis, etc.-all of which increase the cost of manufacturing per die. Therefore, any additional means of increasing yield with less impact on cost have to be exploited. Another possibility of improving product yield is decreasing the defect sensitivity of the layout by design modifications. This can be achieved through co-operation of different areas of process and design development. As shown in Figure 1, from computer- aided failure analysis and defect simulation we can derive process and equipment modifications. For layout-related analysis, the methodology of critical area calculation2 can be used. First, from the analy- sis of a monitor chip, the defect density distribution of a process line is obtained. Then the layout of product chips is analysed in order to estimate the yield, to identify critical structures in the design and to optimize the layout for better yield. In this paper, we report the results of an industrial experiment, which was carried out to demonstrate the sensitivity of manufacturing yield to IC layout. In Section 2, the correlation of various structural design features to yield is presented. In Section 3 we give a brief overview of the defect and yield models used and the methodology of critical area determination. Section zyxw 4 reports the industrial experiment, with results in the determination of defect distribution parameters and in the analysis of different layouts, demonstrating the sensitivity of the critical area analysis. Finally, Section 5 discusses the conclusions that can be drawn from the exper- imental results. 2. CORRELATION OF DESIGN FEATURES AND YIELD The influence of various design features on the yield was investigated. Different products fabricated in the same process, which were designed with full custom and/or semicustom methodology, have been examined. Figure 2 shows the dependence of yield CCC 0748-8017/95/040227-06 @ 1995 by John Wiley & Sons, Ltd. Received October 1994 Revised March 1995