Bae et zyxwvutsrqpon al.: A Single-Chip HDTV A/V Decodcr For zyxwvutsrq Low Cost DTV Receiver 887 zyx A SINGLE-CHIP HDTV A/V DECODER FOR LOW COST DTV RECEIVER Seong-Ok Bae, Seehyun Kim, Seung-Jai Min, Woojin Kim, and Cheol-Hong Min LG Corporate Institute of Technology, DSP Group, Seoul, Korea ABSTRACT In this paper, a single chip HDTV decoder is presented which drastically cut down the cost of HDTV receiver. The cost reduction is achieved by integration of system parser, down-converting video decoder, and multi-mode audio decoder. System designers can also benefit from the features of our decoder which requires only 4Mbytes of SDRAMs(Synchronous DRAM) for decoding HDTV signal and various system-level functions such as IEEE 1394 bus interface, 12C bus controller and on-chip clock recovery function. 1. INTRODUCTION HDTV programs have been on the air since last November in the United States. In spite of high picture quality, the receiver market is not mature yet. Some of major reasons would be high price, insufficient contents and services. Since the monitor constitutes the large portion of the receiver price, the down-conversion set-top box could be a cost- effective solution in HDTV content viewing. PC add-in receiver cards also require a low cost decoder. Much works has been done in developing HDTV decoders [1][2], but no one has integrated fully enough to make the receiver acceptable for the low- end market. A single chip solution for ATSC digital television has been developed. System parser, video and audio decoders are integrated on the chip. To lower the memory.bandwidth, a novel compression algorithm and a memory management scheme have been developed. With these two features, the decoder runs at 54MHz with 4MByte external memory. The architecture of the single chip zyx AN decoder is described in section 2. In section 3, the efforts to reduce memory bandwidth are discussed. Section 4 is devoted to the low power implementation issues in developing the single chip decoder. Finally, conclusion is made in Section 5. 2. OVERALL ARCHITECTURE The HDTV AN decoder is designed to work with the minimum help of an external host processor. When the external host processor issues commands by simply setting command registers in the decoder, the decoder executes transport stream demuxing, decoding, and displaying of audio and video frames. Once the decoder starts, it controls all works necessary for AN decoding and synchronization, so the host processor doesn't need to consume its power in controlling the decoder until PSIP information is updated or closed caption data is arrived. A block diagram of the architecture for the highly integrated HDTV AN decoder chip is illustrated in Fig. 1. The decoder is composed of four major sub-units: System Parser, Audio Decoder, Video Decoder, and SDRAM Controller. TP Demux receives the transport stream data and performs the PID filtering to select the necessary transport packets for decoding. Video Decoder performs MPEG2 MP@HL video decoding based on the novel memory compression algorithm for reconstructed image. The Main Controller controls all internal activities required for video decoding and AN synchronization. Reconstructed image is Manuscript received June 28, 1999 0099 3063/99 $10.00' 1999 IEEE