SampTA 2011 AN ASYNCHRONOUS FIR FILTER ARCHITECTURE COUPLED TO A LEVEL-CROSSING ADC Taha Beyrouthy 1 , Laurent Fesquet 1 , Modris Greitans 2 , Rolands Shavelis 2 , Robin Roland 3 1 TIMA Laboratory, Concurrent Integrated Systems Group, Grenoble, France 2 Institute of Electronics and Computer Science, Latvia 3 CIME Nanotech, Grenoble, France {Taha.Beyrouthy , Laurent.Fesquet}@imag.fr , {modris greitans, shavelis}@edi.lv ABSTRACT This paper presents the architecture of an asynchronous digital signal processing chain, working with non-uniformly sampled data in time. We focus on a Finite Impulse Response filter (FIR) applied to this non-uniform sampled signal obtained from an asynchronous analog to digital converter (A-ADC). The main advantage of combining the asynchronous design with the non-uniform sampling is the drastic reduction of the power consumption, thanks to the reduction of the computational load. Keywords— Asynchronous logic, non-uniform sampling, FIR filter, FPGA. 1. INTRODUCTION Asynchronous logic is well known for its interesting intrinsic properties [6]. It has been proven that this logic improves the Nyquist ADCs performances in terms of immunity to metastable states, low electromagnetic emission or low power consumption. Moreover, non-uniform sampling and especially the level- crossing sampling become more interesting and beneficial when they deal with specific signals like temperature, pressure, electro-cardiograms or speech that evolve smoothly or sporadically. Indeed, these signals are able to remain constant on a long period and to vary significantly during a short period of time. Therefore using the Shannon theory for sampling such signals leads to useless samples that increase artificially the computational load. Classical and uniform sampling takes samples even if no change occurs in the input signal. The authors in [6] show how using the non-uniform sampling technique in ADCs leads to drastic power savings compared to Nyquist ADCs. A new class of ADCs, called asynchronous ADCs (A- ADCs) has been developed by the TIMA Laboratory [2]. This A-ADC is based on the combination of a level-crossing sampling scheme and a dedicated asynchronous logic [4].. The asynchronous logic samples digital signals when an event occurs, i.e. a sample is produced by the A-ADC which delivers non-uniform data in time. This event-driven architecture combined with the level-crossing sampling scheme is able to significantly reduce the dynamic activity of the signal processing chain. Many publications on non-uniform sampling are available in the literature, but to the best of our knowledge none relates to the coupling of an event-driven (asynchronous) logic and FIR filters techniques applied to a non-uniform sampling scheme. This paper presents the implementation of an asynchronous FIR filter using level crossing sampling scheme on an FPGA board (Altera-DE2). The approach has been validated by simulation. This is the first time that such a system is implemented. 2. ASYNCHRONOUS LOGIC Asynchronous logic is well known for its interesting properties such as low electromagnetic emission, low power consumption, robustness. Unlike synchronous logic, where the synchronization is based on a global clock signal, asynchronous logic does not need a clock to maintain the synchronization between its sub-blocks. It is considered as a data driven logic where computation occurred only when new data arrived. This intrinsic property makes the asynchronous logic a good choice to implement data-driven sampling algorithms. In fact, each part of an asynchronous circuit, establishes a communication protocol, with its neighbors in order to exchange data with them. This communication protocol is Figure 1: Handshake protocol is established between two sub-blocks of an asynchronous circuit that need to exchange data between each other