160 IEEE TRANSACTIONS ON ADVANCED PACKAGING, VOL. 33,NO. 1,FEBRUARY 2010 LTCC Spiral Inductor Synthesis and Optimization With Measurement Verification Hsin-Chia Lu, Member, IEEE, Tuck Boon Chan, Charlie Chung-Ping Chen, Member, IEEE, Chia-Ming Liu, Heng-Jui Hsing, and Po-Sheng Huang Abstract—In RF/microwave circuit design, inductor design is one of the most difficult and time-consuming tasks due to the tedious trial-and-error optimization process to achieve the target specifications such as inductance, quality factor and oc- cupied space. This paper brings forward a fast spiral inductor synthesis method, which automatically generates physical layout of inductors according to electrical specifications. By fusion of substrate-aware partial element equivalent circuit (PEEC) model with nonlinear optimization engine, our modeling and synthesis strategies have been verified with industrial field solver and mea- surement results. Our calculation results got less than 7% error for inductance and less than 9% for quality factor as compared to the results from full-wave electromagnetic simulation software. This can provide a fast and good initial inductor design for designer. Index Terms—Inductors, modeling, optimization methods. I. INTRODUCTION I N the realm of analogue circuits, designing high quality inductors—the key passive component—has been a major concern over the past few years. Complementary metal–oxide–semiconductor (CMOS) technology is the first choice for radio-frequency (RF) application, because of its advantages of low cost, mature technology, and easiness to be integrated. However, the lossy nature of silicon limits the implementation of high quality inductors in CMOS technology. An alternative approach to solve this problem could be inte- grating CMOS circuits with passive elements implemented on packaging substrate or discrete surface mounted chip inductors. Surface mount chip inductors can provide large inductance with good quality factor but they take additional space on the printed circuit board thus increase the size and weight of final system. Embedding inductors into packaging substrate such as low temperature co-fired ceramic (LTCC) [1] or integrated passive device (IPD) process using benzo-cyclo-butane (BCB) or polyimide (PI) are some attractive approaches [2]. This approach can reduce size and weight. Although the LTCC process can deliver higher quality inductors, the design process Manuscript received September 06, 2008; revised June 29, 2009. First pub- lished October 30, 2009; current version published February 26, 2010. This work is supported in part by the National Science Council of Taiwan under the Grant NSC 95-2219-E-002-020, NSC 96-2221-E-002-283-MY3 and in part by the National Taiwan University under the Excellent Research Projects 95R0062- AE00-08. This work was recommended for publication by Associate Editor L.-T. Hwang upon evaluation of the reviewers comments. The authors are with the Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan (e-mail: leonardo@ew.ee.ntu.edu.tw). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TADVP.2009.2028636 is time consuming due to the lack of fast and accurate model to estimate inductors’ electrical characteristics. The straightforward inductor optimization approaches are enumeration and binary search based upon exhaustive field solver [3] or simplified circuit model [4]. Other proposed op- timization methods include geometry programming (GP) [5], SQP [6], mesh adaptive direct search (MADS) [7], and implicit space mapping (ISM) [8]. These methods are either based on CMOS inductor model [6], [7] or posynomials (sum of mono- mial) formulas derived from a large CMOS inductor family [5], [8]. With the much larger conductor size and spacing on a typical LTCC process, the circuit models or formulas proposed in these literatures are no longer valid. In [9], an approach of optimizing LTCC inductors using neuron network is proposed. Instead of using circuit models or extracted posynomials func- tions, this method trains the neuron network from measured inductor data which is far too expensive and time-consuming. To reduce the cost of fabrication and long turn around time, [10] use simulated inductor parameters from EM simulation instead of actual measured inductors to train the neural network for inductor synthesis under liquid crystal polymer (LCP) as substrate. Interpolated data from EM simulation are also used to improve the accuracy neural networks. Since the number of metal layers and the dielectric thickness are fixed for a certain semi-conductor fabrication technology nodes, library based approach is a good approach for inductor synthesis. For LTCC process, the designer can choose his own number of layers and dielectric thickness. It is almost impos- sible to build a library for all combination of layer and dielectric thickness. A rapid yet accurate inductance calculation engine is then required for synthesis and optimization. In this paper, we use 2-D meshing in partial element equivalent circuit (PEEC) method [11] to handle the thicker metal in packaging substrate. Nonlinear optimizer is then combined with the PEEC induc- tance calculation engine to optimize the geometry dimensions of the inductor to meet designers’ requirement. Our meshing strategies can capture inductance, skin effects, and proximity effects. With the accurate and efficient inductance calculation engine, we can exploit the powerful optimization algorithms [4]–[8]. Among these algorithms, SQP [6] is one of the most efficient one and is much faster than enumeration algorithm. Although geometry programming [5] could be a powerful solution but it requires both the objective function and constraints are sum of polynomial functions. To figure out the posynomial functions, electrical performances such as inductance and quality factor must be first extracted from large number of fabrication or sim- ulation samples before the curve fitting process. As mentioned 1521-3323/$26.00 © 2010 IEEE