Patterning of pyramidal recesses in (1 0 0)InP substrate P. Eliáš a,⇑ , I. Kostic ˇ b , J. Šolty ´s a a Institute of Electrical Engineering, Slovak Academy of Sciences, Dúbravská cesta 9, 841 04 Bratislava, Slovak Republic b Institute of Informatics, Slovak Academy of Sciences, Dúbravská cesta 9, 845 07 Bratislava, Slovak Republic article info Article history: Received 17 February 2010 Received in revised form 30 June 2010 Accepted 18 August 2010 Available online 22 August 2010 Keywords: Inverted pyramids InP Wet-etching abstract Symmetrical pyramidal recesses were etched into (1 0 0)InP substrate in 3HCl:1H 3 PO 4 at (16 ± 0.05) °C via 20 lm  20 lm square windows opened in InGaAs. The windows had sides aligned in h001i and cor- ners tapered along [0 1 1] and ½0  11. The recesses had each of the four sides at the square edges com- posed of a large ordinary facet (called pyramidal) and a small re-entrant facet. The pairs were identified to be initially close to {1 1 0}/f  110g (pyramidal pairs), i.e. the ordinary pyramidal facets were initially close to (1 1 0), (1 0 1), ð1  10Þ, and ð10  1Þ. However, they deviated towards planes with higher Miller indices with etching duration. The recesses were also confined to etch-stop {0 1 1} and fast-etch- ing {1 1 1}B facets at the [0 1 1] taper edges and etch-stop {2 1 1}A ones at the ½0  11 taper edges. The recesses evolved into sharp inverted pyramids with sub-100 nm extremities at the bottom if etched at least 30 min. The sharpening is possible thanks to the elimination of the etch-stop {2 1 1}A facets via a self-limited etching of the pyramidal pairs. Ó 2010 Elsevier B.V. All rights reserved. 1. Introduction The artificial structuring of semiconductor substrates, realized by localized dry- and wet-etching, lies at the core of any device technology. In III–Vs, such as InP and GaAs, mesas, ridges and grooves are the traditional patterns used for the definition and iso- lation of devices and in patterned epitaxy. The patterns are con- fined to sides whose profiles can range from rounded, containing ensembles of crystallographic facets, to straight ones, defined by a single facet [1–3]. The geometry of the latter is carefully defined to lead during epitaxy to the self-organized growth of quantum wells [4], wires [5,6], and dots [7]. This paper reports on pyramidal recesses exposed in (1 0 0)InP. The InP crystal contains twelve {1 1 0} crystallographic planes that have identical atomic arrangements. Four of them, (1 1 0), (1 0 1), ð1  10Þ, and ð10  1Þ, intersect (1 0 0) at 45° and theoretically define inverted and upright pyramids based in (1 0 0). It was demonstrated previously that mesas confined to pyramidal facets related to (1 1 0)/ð1  10Þ and (1 0 1)/ð10  1Þ pairs can be exposed in HCl via linear etching mask patterns aligned close to h001i [8– 10]. Below is a demonstration showing that flat-bottom and sharp inverted pyramids confined to such facets can be exposed in (1 0 0)InP by etching in HCl via square windows opened in InGaAs etching mask. 2. Experiment The recesses were etched into standard (1 0 0) semi-insulating InP:Fe substrate via a lattice-matched InGaAs layer, prepared by organometallic vapour phase epitaxy. The etching mask material exhibits superior masking properties because InGaAs (1) forms excellent interface with InP and (2) is inert to non-oxidizing HCl solutions, used to etch InP [11]. The patterning of InP substrates through such mask is well defined and highly repeatable [12,13]. The InGaAs etching mask was 120 nm thick, which allowed the ob- server to evaluate the amount of the InGaAs mask undercutting. We assume that as the mask was being undercut, edges of the re- leased (free-standing) sections of the mask may have been sub- jected to some stress. However, we expect it had a negligible influence on the pyramidal recess formation. Windows in the InGaAs layer were opened with complete selec- tivity over InP in 1H 3 PO 4 (85% w/w):1H 2 O 2 (30% w/w):8H 2 O at 25 °C through openings in resist, defined by contact mode optical lithography. The windows were nominally 20 lm  20 lm squares with their sides aligned along h001i (Fig. 1(a)). The squares had their corners tapered along [0 1 1] and ½0  11. Prior to the patterning, samples of the processed substrate were cleaned in acetone, isopropylalcohol and in oxygen plasma, then stripped off of surface oxides in 1HF(40% w/w):4H 2 O for 1 min at room temperature, and dried up in nitrogen flow. They were glued to GaAs holder chips (GaAs is not etched in HCl). The samples were etched in 3HCl:1H 3 PO 4 at (16 ± 0.05) °C during 1, 2, 3, 5, 10, 15, 20, 30, 40, 60, and 80 min in light without agitation. (It was not crucial to keep the etching bath temperature fluctuation so small for this 0167-9317/$ - see front matter Ó 2010 Elsevier B.V. All rights reserved. doi:10.1016/j.mee.2010.08.016 ⇑ Corresponding author. Tel.: +421 2 5922 2695; fax: +421 2 5477 5816. E-mail address: elekelia@savba.sk (P. Eliáš). Microelectronic Engineering 88 (2011) 36–40 Contents lists available at ScienceDirect Microelectronic Engineering journal homepage: www.elsevier.com/locate/mee