SELECTIVE SIMILARITY FUNCTION FOR VLSI ANALOG SIGNAL PROCESSING Jordi Madrenas, Daniel Fernández, Jordi Cosp, Eduard Alarcón, Eva Vidal and Gerard Villar Department of Electronics Engineering. Universitat Politècnica de Catalunya. Jordi Girona 1-3. Campus Nord, mòdul C4. 08034 Barcelona (Spain). e-mail: madrenas@eel.upc.edu ABSTRACT The similarity calculation of two input voltages can be performed in the analog domain by means of a very compact current switch combined with a differential pair stage. Local feed-forward of the current switch allows the circuit to work without the need of any external control ensuring at the same time very high selectivity. The current switch is analyzed by means of its large-signal model, since the first-order small-signal model is not enough to obtain insight on its behavior. The obtained peak cell circuit is applied to bioinspired gray-level image segmentation focal-plane processor. Other direct applications of the current switch are full-wave differential rectifiers and two-input maximum/minimum circuits. 1. INTRODUCTION The analog VLSI implementation of a class of neuromorphic image segmentation algorithms [1] demands, for gray-level processing, selective similarity functions with maximum response when two input voltages match and progressive reduction as they differ. The existing local function circuits (e.g. bump function [2]) are not suitable for this application because of the flat response around the maximum. Therefore, to obtain selectivity around the maximum, a function that changes suddenly its slope, i.e., with a peak shape response, is sought. This way, the segmentation system can better distinguish among the pixels' similarity. This kind of function is found in maximum-minimum circuits and full-wave rectifiers. Although a full-wave rectifier [3-5] or max-min circuits [6-8] could be selected and adapted to fulfill the requirements, existing architectures are either complex circuits and/or applied to non-differential signals, whereas a compact and differential solution is desired in this application. In the paper we present a very compact, high-performance circuit based on 4 cross-coupled MOS transistors that selects the maximum and minimum of two input currents that can be generated by a previous differential amplifier stage when voltage input is available. In next section, the current switch is presented and analyzed, and its simulation results are shown in Section III. In Section IV, the circuit of a peak cell, a selective similarity function, is discussed and simulations are presented. In Section V the application of the peak cell to an image segmentation IC is summarized. Finally, we conclude in Section VI. 2. THE CURRENT SWITCH Fig. 1a shows the current switch operating principle. It is based on redirecting the maximum and minimum input currents to the corresponding output lines. Two pairs of MOSFETs are controlled so that the maximum and minimum of input currents I 1 and I 2 are directed to I MIN and I MAX output lines, respectively. The key point with this simple idea is how to control the switches. Usually, MOS gates have been controlled by means of a voltage comparator that controls the switch [9]. In our approach, voltage comparison is intrinsically performed at the same input nodes of the switch. As shown in Fig. 1b, 4 transistors implement the switches without the need of any control circuits. The circuit can be analyzed as two cross-coupled current mirrors connected to the input and output nodes. Mirror M 1A -M 2B implements the parallel switches and mirror M 2A -M 1B , the cross-coupled ones. All transistor sizes are assumed to be identical. (a) (b) Figure 1. a) Operating principle; b) CMOS max-min current switch. Provided that all transistor sources are fixed to the same constant voltage (V REF in Fig. 1b) and setting V REF = 0 for analysis simplicity, input voltages V 1 and V 2 control the gate-source transistors voltage and thus their operating conditions. Applying Kirchhoff Current Law, considering ideal saturated transistors and ideal current mirrors, I 1 I 2 I MAX I MIN I 1 I 2 I MAX I MIN I 1 I 2 I MIN I MAX V 1 V 2 M 1A M 2A M 2B M 1B V REF V REF I 1 I 2 I MIN I MAX V 1 V 2 M 1A M 2A M 2B M 1B V REF V REF 3926 0-7803-8834-8/05/$20.00 ©2005 IEEE.