1 Postgrowth Control of the Quantum-Well Band Edge for the Monolithic Integration of Widely Tunable Lasers and Electroabsorption Modulators Erik J. Skogen, Student Member, IEEE, James W. Raring, Jonathon S. Barton, Steven P. DenBaars, and Larry A. Coldren, Fellow, IEEE Abstract— We describe a quantum well intermixing process for the monolithic integration of various devices, each with a unique band edge. The process involves a single ion implant followed by multiple etch and anneal cycles. We have applied this method to design and fabricate widely-tunable sampled- grating DBR lasers with integrated electroabsorption modulators. The devices employ three unique band edges, and demonstrate exceptional tuning, gain, and absorption characteristics. Index Terms-- Ion implantation, Laser tuning, Semiconductor lasers, Wavelength division multiplexing. I. INTRODUCTION M onolithic integration of widely-tunable lasers with supplementary optoelectronic components offer cost reduction, improved performance, and added functionality over existing fixed wavelength components used in optical networks. The sampled-grating (SG) distributed Bragg reflector (DBR) laser is ideal for this purpose, as the lithographically defined mirrors allow for the manipulation of light on chip. The difficulty arises when optimization requires each of the integrated components to possess a unique band edge. Limited by the one-dimensional growth platform used to produce the epitaxial material, the push for monolithic- integration has lead to either compromises in device design or complex processing to achieve the goals. The solution is the development of a manufacturable wafer- scale process, which allows for the precise control of the band edge across the wafer. In this paper, we describe a process, and present device results using QWI to tune the band edge of the quantum well (QW) active region across the wafer achieving multiple unique QW band edges to fabricate widely-tunable SG-DBR lasers with integrated electroabsorption modulators (EAM). There are a few general guidelines to bear in mind when implementing a method for monolithic integration. First, the method used should not be prohibitively time consuming or expensive. This is the key to realizing the cost reduction over existing discrete components. Second, the integration should not lead to device compromises. This is a difficult task due to the fact that each discrete device was designed with a single function in mind and therefore the device structure evolved on an individual basis. However the integrated component must only perform as intended, it does not necessarily need to match the performance of a discrete device. This affords some flexibility in the design of the device in terms of the device structure, possibly allowing devices with differing functionalities to be fabricated using the same growth and processing platform. Lastly, the process complexity should remain constant as the number of integrated components increases. An additional processing step or the substitution of one step for one that is more complex can increase the manufacturing cost and, in the case of complex processing/growth can lead to yield reduction. There has been some great success in producing simple photonic integrated circuits (PICs) based on various methods. Such methods include but are not limited to butt-joint regrowth [1], selective area growth (SAG) [2], and the use of offset QWs [3]. The first, butt-joint regrowth involves the selective removal of waveguide core material followed by the regrowth of an alternate waveguide core using different material composition. This process is inherently difficult involving a precise etch of the original waveguide core, followed by a regrowth of waveguide material with composition and thickness variables. Another process, the SAG process, involves selective growth using a mask. In this process a mask is patterned on the surface of the wafer prior to epitaxial growth. The geometry of the mask has a role in determining the growth near the vicinity of the mask and can be used to obtain different compositions and thickness across the wafer. This method is useful in fabricating several band edges across the wafer, but due to the fact that the thickness changes for each of these regions, the optical confinement factor is not at an optimal level in each section. The use of offset QWs, where the QWs are situated above the waveguide and selectively removed in various regions, has been used with great success in fabricating various integrated structures [3, 4, 5, 6]. However, the use of offset QWs limits the devices to one of two band edges, not allowing for the flexibility necessary for the fabrication of complex PICs. Furthermore, the vary nature of the offset QW design does not allow for the optimal optical mode overlap with the QWs, Manuscript received February 14, 2003.; revised July 22, 2003. E. J. Skogen and L. A. Coldren are with the Electrical and Computer Engineering Department, University of California, Santa Barbara, Santa Barbara, CA 93016 USA (e-mail: Skogen@engineering.ucsb.edu). J. W. Raring, J. S. Barton, and S. P. DenBaars are with the Materials Department, University of California, Santa Barbara, Santa Barbara, CA 93106 USA.