772 IEEE ELECTRON DEVICE LETTERS, VOL. 27, NO. 9, SEPTEMBER 2006 RF Split Capacitance–Voltage Measurements of Short-Channel and Leaky MOSFET Devices E. San Andrés, L. Pantisano, J. Ramos, S. Severi, L. Trojman, S. De Gendt, and G. Groeseneken Abstract—In this letter, the feasibility of split-capacitance– voltage (C –V ) measurements in the RF range is demonstrated. These RF/split-C –V measurements show excellent agreement with the values obtained by the low-frequency conventional tech- nique but without presenting any noticeable degradation due to gate leakage. Index Terms—Capacitance measurement, MOSFET, RF, ultra- thin gate dielectric. I. I NTRODUCTION T HE CONVENTIONAL split-capacitance–voltage (C–V ) measurement at low frequency [1] has been successfully demonstrated as a necessary tool to extract basic gate stack parameters such as equivalent oxide thickness (EOT), flat-band voltage V fb , channel doping, and mobility [2], [3]. However, this tool has not been demonstrated yet for the most advanced devices of interest in the semiconductor industry. The test of leaky and short-channel devices poses a dramatic challenge for basic gate stack characterization due to the limited sensitivity of conventional metrology apparatus and the long measuring times needed. The leakage effect can be minimized by increasing the capacitance signal through the increase of the measurement frequency, but to do this correctly, it is imperative to use microwave techniques. The gate capacitance measurement at high frequency in the presence of high leakage has already been demonstrated by Schmidtz et al. [4] by using MOSFETs connected as two-port amplifiers, with the source and bulk tied to the ground. By grounding the drain port, they were able to measure the gate-to-all capacitance C ga at frequencies in the range of 0.5–1 GHz for very leaky and small devices. In the literature, this method has been denominated as RFCV [3], [4]. However, due to the layout of the connections (source and bulk Manuscript received March 28, 2006; revised June 6, 2006. This work was supported in part by the Interuniversity Microelectronics Centre (IMEC) Industrial Affiliation Program on High-k and Metal Gates and in part by the Spanish MEC under Contract TEC 2004-1237/MIC. The stay of E. San Andrés in IMEC was supported by the Secretaría de Estado de Universidades e Investigación of the Spanish MEC under a postdoctoral grant. The review of this letter was arranged by Editor A. Wang. E. San Andrés is with the Departamento de Electricidad y Electrónica, Facultad de Ciencias Físicas, Universidad Complutense, 28040 Madrid, Spain (e-mail: esas@fis.ucm.es). L. Pantisano and J. Ramos are with the Interuniversity Microelectronics Centre, 3001 Leuven, Belgium. S. Severi, L. Trojman, and G. Groeseneken are with the Interuniversity Microelectronics Centre, 3001 Leuven, Belgium and are also with the Depart- ment of ESAT, Katholieke Universiteit Leuven, 3001 Leuven, Belgium. S. De Gendt is with the Interuniversity Microelectronics Centre, 3001 Leuven, Belgium and also with the Department of Chemistry, Katholieke Universiteit Leuven, 3001 Leuven, Belgium. Digital Object Identifier 10.1109/LED.2006.881089 Fig. 1. Schematic drawing of the connections of the device to the network analyzer. The voltages and the several current components are included in the graph. shorted), C ga could not be separated into its two components, namely 1) the gate-to-bulk or accumulation capacitance C gb and 2) the gate-to-channel or inversion capacitance C gc . The accurate determination of these capacitances is imperative to determine the average channel mobility [2], [3]. In this letter, we show how RFCV techniques can be applied to measure C ga , C gb , and C gc simultaneously at frequencies well above the megahertz range using an optimized layout. This technique extends the split-C–V method to very leaky or very small transistors of interest for advanced gate stacks, thus, enabling carrier mobility extraction. We will denominate this technique as RF/split-C–V . II. EXPERIMENTS The studied devices are n-channel MOSFETs fabricated in a conventional CMOS flow. The SiO 2 gate dielectric has a thick- ness of 1.8 nm. The gate electrode is a fully silicided (FUSI) NiSi gate contact [6]. The leakage of these devices is rather high (≈ 250 A/cm 2 at a gate voltage of -3 V). The precise optimization and control of the MOSFET layout and the pad configuration are crucial. The layout of the RFCV devices [5] was optimized in order to minimize the series resistance, which would influence the admittance measurements at high frequency. The active area of the device is surrounded by ap + guard ring, which acts as a surface substrate contact, thus, dramatically reducing both the RF signal return path [7] and the substrate contact resistance to ≈ 30 Ω. Each test structure has 20 fingers to increase the input capacitance. The width of each finger is 11 μm, and the nominal lengths are 1, 0.25, 0.20, and 0.15 μm. The contact pad config- uration is very important and has been designed for com- patibility with ground–signal–ground (GSG) probes (Fig. 1). The gate is connected to port 1, while the source and drain are shorted together to port 2. The substrate contact is the 0741-3106/$20.00 © 2006 IEEE