Learning CMOS Logic Gate Design by Exploring Switch Network Domain Renato P. Ribas 1 , Vinicius Callegaro 1 , Leomar Soares da Rosa Jr. 2 , André I. Reis 1 1 Federal University of Rio Grande do Sul - UFRGS, Porto Alegre, RS, Brazil 2 Federal University of Pelotas - UFPel, Pelotas, RS, Brazil 1 E-mail: 1 {rpribas,vcallegaro,andreis}@inf.ufrgs.br, 2 leomarjr@inf.ufpel.edu.br Abstract Switch networks are the basis for digital electronic design regardless the current technology applied. However, such topic has not been deeply explored in CMOS integrated circuits due to particularities and electrical restrictions of CMOS gates, which concentrate in quite simple and basic functions. This paper proposes a new pedagogical way for learning logic gate design starting from switch network building. Next, different CMOS design styles are presented according to the network (logic planes) combinations, i.e., the gate topology. By doing so, such bottom-up acquiring of concepts focuses initially only on the functional behavior of switch arrangements, treating afterwards the gate topology and electrical characteristics associated to each logic family. An innovative CAD environment, called SwitchCraft, has been developed to assist such novel educational methodology. Keywords Switch network, CMOS, logic gate, digital design, CAD, Boolean function. 1. Introduction In electrical and computer engineering (ECE) and computer science (CS) the design of digital circuits represents one of the fundamentals of students’ learning. The understanding of this topic starts from building individual logic gates to generate afterwards more complex functional blocks and circuits. Nowadays, integrated circuit (IC) is certainly the most applied technology in electronic products, being in a great majority represented by CMOS design styles [1-3]. Different CMOS logic families have been frequently proposed in the literature, including static and dynamic topologies, single-output and differential structures, multiple- output gates, pass-transistor logic (PTL) approaches, and a large number of variations [4-10]. Undergraduate lectures and textbooks usually introduce this subject taking into account the conventional static CMOS topology [1-3]. It is built based on pull-up (PU) PMOS and pull-down (PD) NMOS disjoint planes, being generally composed by series (S) and parallel (P) transistor arrangements. At first, CMOS inverter gate is presented, since it corresponds to the simplest arrangement of transistors in a single logic gate structure. Next, NAND and NOR gates are addressed to illustrate and discuss the series and parallel device associations. It aims to detail the impact of transistor stacking in the electrical performance of CMOS gates. Simple AND-OR-INV (AOI) gates are sometimes treated, while more complex gates are barely mentioned. Other logic families, like PTL [9,10], dynamic domino [4,6], DCVSL [7,8], and others [1-3,5] are normally introduced by analyzing directly their electrical behavior, advantages and limitations, without paying much attention on the logic plane generation. Indeed, in this classical pedagogical methodology, the logical part of gates, i.e., logic planes composed by switch networks have received little attention being even just ignored in undergraduate courses. Therefore, such an interesting design space of gate optimization is not realized by students. Furthermore, as different logic families and gate topologies are presented separately, the general overview of CMOS design styles is not actually acquired by future IC designers. This work proposes a new way to broach this subject. First of all, switch networks are explored in terms of methods of generation and optimization, regardless the construction of logic gates. It starts from building (and analyzing) individual switch networks, where the functional information is represented by the on/off binary states of logic paths between two or more terminals. Thus, the network arrangement and functionality can be given directly by Boolean expressions. It can be also defined and evaluated through graph data structures, like binary decision diagrams – BDDs [11]. Even though the same functionality can be implemented by different switch arrangements, it may lead to distinct profiles and characteristics. Those particularities might be optimized according to different criteria, such as the minimum switch count, the minimum number of switches in stack, and the polarity of input variables. Once switch networks have been well understood, these ones can be then combined to build logic gates. According to the strategies of connecting such networks and the eventual use of pre-fixed PU and/or PD circuitries, a large variety of logic families with particular electrical behavior (delay and power dissipation) are resulted [1-10]. At this stage of learning, the functionality of gates is no more the main issue, but instead the circuit voltages and currents relationship, which are strictly related to each type of topology. This purpose represents a new way to teach and learn about logic gate design, and for that an innovative CAD environment, called SwitchCraft, has been developed to support such pedagogical methodology [12]. This environment can be seen in four basic parts: (a) logic definition, (b) switch network generation, (c) logic gate construction, and (d) performance analysis. From the authors’ knowledge, there is no similar tool proposed in the academic literature, or available in the Web (open source or freeware tool) and from CAD vendors. In order to demonstrate the richness of the switch network field, usually neglected in digital circuit courses, a short 978-1-4673-0840-3/12/$31.00 ©2012 IEEE 60 Interdisciplinary Engineering Design Education Conference