Direct Imprinting of Dielectric Materials for Dual Damascene Processing Michael D. Stewart *a,b , Jeffery T. Wetzel c , Gerard M. Schmid d , Frank Palmieri a , Ecron Thompson b , Eui Kyoon Kim a , David Wang b , Ken Sotoodeh c , Kane Jen a , Stephen C. Johnson a , Jianjun Hao a , Michael D. Dickey a , Yukio Nishimura a , Richard M. Laine e , Douglas J. Resnick f , C. Grant Willson a a Dept. Chemical Engineering, The University of Texas at Austin, Austin, TX 78712 b Molecular Imprints, Inc., 1807-C W. Braker Lane, Austin, TX 78758 c ATDF, Inc., 2706 Montopolis Drive, Austin, TX 78741 d Molecular Foundry, Lawrence Berkeley National Lab, 1 Cyclotron Road, Berkeley, CA 94720 e Dept. Chemistry, University of Michigan, Ann Arbor, MI 48109 f Motorola Labs, 7700 South River Parkway, Tempe, AZ 85284 ABSTRACT Advanced microprocessors require several (eight or more) levels of wiring to carry signal and power from transistor to transistor and to the outside world. Each wiring level must make connection to the levels above and below it through via/contact layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around twenty process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. By using an imprint template with two levels of patterning, a single imprint lithography step can replace two photolithography steps. Further efficiencies are possible if the imprint resist material is itself a functional dielectric material. This work is a demonstration of the compatibility of imprint lithography (specifically SFIL) with back-end-of- line processing using a dual damascene approach with functional materials. Keywords: SFIL, dual damascene, nanoimprint lithography, multi-tier template, interconnect 1. INTRODUCTION Advanced microprocessors require several (eight or more) levels of wiring in addition to the transistor gate level. Each wiring level is stacked over the previous level with connections to the levels above and below made through via layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via/contact level simultaneously, and thereby reduces the total number of processing steps. A damascene approach is a necessity when copper is the conductor metal because there are no effective plasma etch processes for copper. By patterning two layers and then filling both with metal, the dual damascene approach (of which there are several variations) reduces the total number of process steps; however this method still requires around twenty process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires less than half as many steps as the standard photolithographic dual damascene approach. By using an imprint template with two levels of patterning, a single imprint lithography step can replace the two separate photolithography steps. In addition to directly reducing the total number of processing steps, patterning two levels simultaneously removes some of the most difficult aspects of the current dual damascene approaches, such as performing the second photolithography step over the topography generated by the first photolithography step. Also alignment of the via and upper wiring level is performed at the template fabrication stage, so only a single alignment step is required during the device manufacturing stage. * email: mstewart@militho.com