IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 47, NO. 6, JUNE 2012 1469 A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing Ming-Hsien Tu, Jihi-Yu Lin, Ming-Chien Tsai, Chien-Yu Lu, Yuh-JiunLin, Meng-Hsueh Wang, Huan-Shun Huang, Kuen-Di Lee, Wei-Chiang (Willis) Shih, Shyh-Jye Jou, Senior Member, IEEE, and Ching-Te Chuang, Fellow, IEEE Abstract—This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-inter- leaving architecture, which can reduce multiple-bit upsets in a single word and enhance soft error immunity by employing Error Checking and Correction (ECC) technique. The proposed 9T SRAM cell is demonstrated by a 72 Kb SRAM macro with a Neg- ative Bit-Line (NBL) Write-assist and an adaptive Read operation timing tracing circuit implemented in 65 nm low-leakage CMOS technology. Measured full Read and Write functionality is error free with V down to 0.35 V ( 0.15 V lower than the threshold voltage) with 229 KHz frequency and 4.05 µW power. Data is held down to 0.275 V with 2.29 µW Standby power. The minimum en- ergy per operation is 4.5 pJ at 0.5 V. The 72 Kb SRAM macro has wide operation range from 1.2 V down to 0.35 V, with operating frequency of around 200 MHz for V around/above 1.0 V. Index Terms—Low power, low voltage, negative bit-line (BL), subthreshold SRAM cell, timing tracing. I. INTRODUCTION R ECENTLY, the demand for ultra-low power dissipation battery-operated devices is increasing. If the perfor- mance at low supply voltage ( ) can still meet the system requirements, the system power dissipation can be reduced significantly by scaling down the supply voltage. Fig. 1 shows the measured oscillation frequency, power dissipation and en- ergy per oscillation of a 399-stage NAND-type ring oscillator using 65 nm low leakage CMOS process with threshold voltage ( ) around 0.5 V. The total power and leakage power decrease drastically with scaling, and leakage power dominates the total power in deep subthreshold region even in low leakage process. Total Energy per oscillation decreases Manuscript received September 23, 2011; revised January 23, 2012; ac- cepted January 25, 2012. Date of publication April 13, 2012; date of current version May 22, 2012. This paper was approved by Associate Editor Peter Gillingham. This work was supported in part by the Ministry of Economic Affairs (99-EC-17-A-01-S1-124), and the Ministry of Education under the ATU program. The authors are with the Electronics Engineering Department and Institute of Electronics, National Chiao Tung University, Hsinchu, 300 Taiwan (e-mail: minghsien.ee95g@gmail.com). Y.-J. Lin, M.-H. Wang, H.-S. Huang, K.-D. Lee, and W. Shih are also with Faraday Technology Corporation, Hsinchu, Taiwan. Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/JSSC.2012.2187474 Fig. 1. Measured (a) oscillation frequency, power, and (b) energy per oscilla- tion of 399-stage NAND-type ring oscillator versus supply voltage. first with scaling. However, as the leakage energy starts to dominate with near/below the threshold voltage, a minimum energy point is formed near the threshold voltage. A circuit can achieve ultra-low power dissipation by operating in the subthreshold region, but the circuit must face the challenges of significantly degraded Ion/Ioff ratio and the large Process, Voltage, Temperature (PVT) variations in the subthreshold region. For example, typical Ion variation in super-threshold region is less than a factor of 2, while that in subthreshold region is several orders of magnitude. 0018-9200/$31.00 © 2012 IEEE