International Journal of Computer Applications (0975 – 8887) Volume 61– No.3, January 2013 1 Speeding-up Phase-Locked Loops based on Adaptive Loop Bandwidth Dina M. El-Laithy Communications Engineering Department Modern Academy of Engineering and Technology Cairo, Egypt Abdelhalim Zekry Communications Engineering Department Faculty of Engineering Ain shams University Cairo, Egypt Mohamed Abouelatta Communications Engineering Department Faculty of Engineering Ain shams University Cairo, Egypt ABSTRACT This paper describes three techniques for controlling the loop filter of the PLL for high operating speed. The proposed fast- locking PLL reduces the pull-in time and enhances the switching speed, while maintaining better noise bandwidth. Extended loop bandwidth enhancement is achieved by the adaptive control on the loop filter resistances. This work differs from previously published results in that it presents a comprehensive study for modeling, circuit simulation and practical circuit implementation of a 2nd order PLL with loop filter control for speeding-up the PLL. The overall improvement in performance of the proposed PLL is evaluated and compared with the conventional PLL. An industrial CMOS IC is used to implement the PLL. General Terms Electronic design, Communications, Simulation, Hardware. Keywords Phase locked loop, speeding-up, adaptive bandwidth, natural frequency, settling time 1. INTRODUCTION Phase-locked loops (PLLs) have been used in many applications ranging from communications, radar to automobiles. In the recent past, digital phase-locked loops have been widely used in high-performance microprocessors and high-speed digital communication systems as clock generators [1],[2]. As the speed of these systems increasing, the PLLs with higher operating frequency and lower jitter are in demand. So in nearly all the PLL applications, it is required to generate low noise while achieve fast settling time. The settling time is largely determined by the loop bandwidth. In some applications, the loop bandwidth should be made as narrow as possible to minimize output phase jitter due to external noise, resulting in an elongated settling time. One of the solutions to this problem is the adaptive PLL using a wide bandwidth in the out-of-lock state and switching to a narrow bandwidth as the loop settles. With the adaptive PLL, one could speed up the settling process while ensuring sufficient reference feed-through attenuation for low output noise. For many adaptive PLL’s in literature [3-5], the loop bandwidth enhancement is achieved by increasing the charge pump current and/or increasing the loop gain [6]- [8],[11]-[14]. However, the loop bandwidth is still constrained by the reference frequency for loop stability considerations. Another method of loop bandwidth enhancement is achieved by using a nonlinear loop filter instead of a conventional loop filter [9]. But it is difficult to implement. To expand the loop bandwidth even further, a new adaptation scheme is proposed that not only increases the bandwidth, but also gives good noise performance. This paper describes three improved acquisition techniques designs and it is organized as follows: Section 2 presents the detailed circuits of the proposed PLL for speeding- up acquisition. The simulation results are discussed in Section 3. Section 4 illustrates the experimental results. The conclusions are given in Section 5. 2. OPERATING PRINCIPLE OF THE PROPOSED PLL FOR SPEEDING-UP ACQUISITION A conventional PLL is shown in Fig. 1. It is composed of an XOR phase detector, a loop filter and a voltage-controlled oscillator. The first-order loop filter is composed of the resistors R 1 and R 2 and the capacitor C 1 . The damping factor and natural frequency are approximately expressed as [10]   =               and ζ=        (1) Where K d is the phase detector gain and K o is the gain of the VCO. The bandwidth of a PLL is often specified by the 3-dB corner frequency ω 3db and it is expressed as [10]:   =               (2) For a damping factor ζ = 0.7, ω 3db becomes ω 3db = 2.05 ω n , which is about twice the natural frequency. From Eq. (1) and Eq. (2) to speed-up PLL, the loop bandwidth enhancement is achieved by increasing the natural frequency ω n by reducing the time constants of the loop filter. Fig 1: Conventional PLL