International Journal of Scientific and Research Publications, Volume 6, Issue 5, May 2016 10 ISSN 2250-3153 www.ijsrp.org Comparative Analysis of Existing Clock Gating ALU Vandana Prajapati, Uday Panwar Prajapativandana8517014@yahoo.com,panwaruday1@gmail.com Department of Electronics and Communication Sagar Institute of Research & Technology, Bhopal, India Abstract- Digital world multimedia and DSP based applications work on certain clock pulse and as we know, clock signal. The clock signal consumes maximum applied power and this is a major drawback in digital synchronous circuit. Clock gating is an important technique for reducing the dynamic power losses in digital circuits. In a typical synchronous circuit such as the general purpose ALU multimedia, only a portion of the operating circuit is active at any given point of time and the other circuits remain inactive. Hence, by making the other circuits inactive selectively, the unnecessary power dissipation can be avoided. By using this approach dynamic power losses can therefore be minimized. The new proposed work implements another gated clock technique by using T& D flip flop and making comparative analysis between various gating clock techniques. This approach of minimizing dynamic power is implemented by using Artix-7 and Spartan-6 with 45nm and 40nm FPGA technology respectively. Index Terms- DSP based application, dynamic, clock gating, ALU multimedia I. INTRODUCTION ow-a-days, the power-sensitive or low power dissipation devices are required and the demand of these types of devices has grown significantly. This tremendous demand mainly initiated due to the need for low power consumption and small size digital devices have aggressively dominated successive technology generations. The power has been continuously reduced by improving the implementation of technology and design. The power dissipation can reduced by use of integrating circuit (IC) .The circuit level as well as system level technology are also required to be improved for lower power dissipation. Further, the power dissipation can be reduced by applying the scaled voltage. But the scaled voltage supply limits the possibility of high performance. Hence, the scaling of supply voltage alone may not be sufficient to reduce the power dissipation, which is more important only for power-sensitive applications. Clock signal is main life line for digital circuit operation. Clock signals are synchronizing signals that provide timing references for computation and communication in synchronous digital systems. Synchronization of signal is a major drawback in digital circuits which causes the dynamic power dissipation. Traditionally, the demand for high performance was addressed by increasing clock frequencies with the help of technology scaling. Generally the dynamic power occurs due to clock synchronization and on-off operation of the clock signal. A very clear example of this trend is the recent move towards multi-core architectures for processors [1]. Thus innovative clocking techniques for decreasing the power consumption of the clock networks are required for future high performance and low power designs. Electronic design is the software to design the electronics system the EDA, mostly used to print the CRT integrated circuit. The most important parameters are area, power, and performance. Area can be found in terms of gate count and transistor count and final chip area optimization is done with the help of positioning placement routing. The power optimization analysis which depends mainly on logic level area of the chip, routing cost and many more factors. Also the performance of the electronics system design depends upon gain logic levels, working frequencies and temperature. These parameter lies between 8 different abstraction levels of the design to make it optimal over the all reliable features on EDA tool which may or may not always be a practical solution. To reduce power consumption, to start the proper planning & register transistor (RTL) design in this paper, we use some stream techniques that can be used at the article coding stage that will consume less power than the other technique and keep the basic design unchanged. Fig.1 gated clock generation This approach first presents review on various clock gating technique and also make a comparative analysis of those clock gating techniques on some synchronous digital device like ALU (Arithmetic logical unit). Also it will introduce a new clock gating approach that will have low dynamic power losses. II. APPLICATIONS OF GATED CLOCK 1- All sequential circuit. 2- Memory processing 3- Registers & counters. 4- Data processing. 5- Arithmetic and logic units. III. REVIEW CLOCK GATING N EN CLK FGC GC OPERATIONAL UNIT