Samaher Al-Hothali Department of Computer Science and Engineering, Yanbu University College, Saudi Arabia. Safeeullah Soomro Institute of Business and Technology, Biztek, Karachi, Pakistan. Khurram Tanvir Ruchi Tuli Department of Computer Science and Engineering, Yanbu University College, Saudi Arabia. The computational systems (multi and uni-processors) need to avoid the cache coherence problem. The problem of cache coherence is solved by today's multiprocessors by implementing a cache coherence protocol. The cache coherence protocol affects the performance of a distributed shared memory multiprocessor system. This paper discusses several different varieties of cache coherence protocols including with their pros and cons, the way they are organized, common protocol transitions, and some examples of systems that implement those protocols 1. INTRODUCTION ABSTRACT Journal of Information & Communication Technology Vol. 4, No. 1, (Spring 2010) 01-10 The material presented by the authors does not necessarily portray the viewpoint of the editors and the management of the Institute of Business and Technology (Biztek) or Computer Science and Engineering, Yanbu University College, Saudi Arabia. JICT is published by the Institute of Business and Technology (Biztek). Ibrahim Hydri Road, Korangi Creek, Karachi-75190, Pakistan. * C Shared-memory multiprocessors have been considered for research quite considerably. Shared memory multiprocessors are famous because of the simple programming model they implement. Address space is shared among multiprocessors so that they can communicate to each other through that single address space. Same cache block in multiple caches would result in a system with caches because of sharing of data. This problem doesn't affect the read process but for writes when one processor writes to one location, this change has to be updated to all caches [1]. Cache coherence is a term that refers to ensure consistent data in all caches in case of data write. A distributed algorithm is used to tackle the cache coherence problem known as cache coherence protocol [1]. There are different cache coherence protocols that differ from each other in the scope of places that are updated by write operation. These protocols can impact the performance of a multiprocessor system which is mostly hard to estimate. The performance of a system is directly proportional to the latency of microprocessor accesses. Snoopy and Directory Based Cache Coherence Protocols: A Critical Analysis Keywords : Cache coherence, Snoopy protocols, Directory-based protocols, Shared memory, coherence problem. * * * * * Samaher Al-Hothali : alhothali.samaher@gmail.com * Khurram Tanvir : khurram.tanvir@yuc.edu.sa * Ruchi Tuli : ruchi.tuli@yuc.edu.sa * Safeeullah Soomro : afeeullah.soomro@biztekian.com