A Survey of Testability Measurements at Various Abstraction Levels Naghmeh Karimi + , Pedram Riyahi * and Zainalabedin Navabi + Electrical and Computer Engineering + University of Tehran * Northeastern University naghmeh@cad.ece.ut.ac.ir, priahi@ece.neu.edu, navabi@ece.neu.edu Abstract: The new EDA tools such as high level automatic synthesis and design analysis programs require measurement of testability at one or more levels of abstraction. Depending on the application and the level of the input hardware description, we may need to measure testability of a design at the gate, RTL or behavioral level. This paper presents a survey of various testability methods at these levels. In the last section of this paper, we compare these methods for their applications, speed and complexity of algorithms. 1. Introduction With the fast growth of the VLSI technology, VLSI testing problem has gained critical significance. By applying a Design For Test (DFT) technique on a design, its testability will be improved, although it’s area and delay will be increased. In order to balance these metrics the testability measurement techniques must be considered carefully. In this paper the approaches have been classified according to design abstraction levels. We will discuss testability analysis methods at the gate, Register Transfer and behavioral levels of abstraction. The last section in this paper compares various methods and presents application of these methods in various EDA tools. The reminder of the paper is organized as follows. Section 2 presents an overview of testability analysis methods and measures. Then Section 3 presents some gate level testability analysis methods. The testability analysis techniques at the RT level are described in Section 4; Section 5 discusses the corresponding methods at the behavioral level. Finally Section 6 presents applications of various testability analysis methods and compares the testability methods at different levels of abstractions. 2. Testability Analysis Testability analysis is a way of showing how easy or how hard it is to test a circuit. Testability analysis is not data dependent (test data) and is only determined by the circuit structure or description. This makes the testability an intrinsic property of a circuit. The testability metrics are related to the fault coverage of a design and they are used to measure the fault sensitization and fault propagation cost during test generation. Testability analysis can be done at the gate, Register Transfer (RT), or behavioral levels of abstraction. At the gate level, testability of a design is measured by controllability and observability. Controllability reflects the cost of setting up a specific value on a line, and observability reflects the cost of observing a specific value of a line. At the RT level, testability is mainly measured by controllability and observability at the level of vectors and RT level components. Behavioral testability is a measure of how various parts of a high- level code, or blocks of code, can be reached. Testability measurement at the lower levels of abstraction is more accurate with a higher processing cost. On the other hand, testability measures at the higher levels involve approximations based on the topology of the circuit or coding style. 3. Gate Level Testability Gate level testability is measured using a netlist of the circuit being analyzed. Several techniques have been proposed to measure testability at the gate level. The early work in testability analysis at this level can be seen in References 1 to 3. In these approaches the testability of each line of a design is related to its distance from the primary inputs or the primary outputs. The controllability is related to the distance of that line from the primary inputs and the observability is related to the corresponding distance from the primary outputs [4]. Although these metrics are not precise enough to demonstrate the design testability, they are used very frequently because of simplicity of computations. Some known approaches in this level are SCOAP [2], TMEAS [5-6], COP [7], LEVEL and CAMELOT [8-9], VICTOR and TESTSCREEN [11-12]. 3.1 Generic Methods Generally, many gate-level testability techniques are based on measuring 0-controlability, 1-controllability and observability parameters. In these methods v- controllability is the probability of setting a line to the