This work is partially supported by the research project No. 9(5)/ 2010- MDD dt. 23/1/2011, sponsored by the DeitY, Govt. of India Abstract– This paper presents a reconfigurable Network-on- Chip (NoC) architecture built around mesh topology. It provides the facility of changing the attachment of cores to local routers across applications. Applications share cores, but communication pattern between them may vary. Compared to many other reconfigurable NoCs, our architecture needs only about 0.2% extra area overhead than simple mesh. Application mapping and reconfiguration policy have been developed using Integer Linear Programming (ILP) and heuristic for the proposed topology. It has been shown that the reconfiguration strategy could improve communication costs of applications significantly which often resulted in improved latency and energy values, keeping throughput unaffected. Keywords- Communication cost, Reconfiguration, Integer Linear Programming I. INTRODUCTION Reconfigurable computing essentially utilizes the same set of system resources for applications to run at different instants of time. A Network-on-Chip (NoC) contains a number of cores accomplishing tasks of applications. As different applications have different functionalities, the inter-IP communication characteristics can be very different across the applications. In general, a NoC that is designed to run exactly one application does not necessarily meet the design constraints of others, even if a number of cores are common between them. A reconfigurable computation in such a topology essentially means designing the NoC so that the performance of all applications become acceptable. In this paper, we propose a reconfigurable architecture for regular mesh based NoCs by taking basic architecture from [7], where core clusters are connected to each router. In contrast, we restrict the number of cores per router to one. Our proposed architecture enables the changes in the positions of the cores dynamically to match communication patterns of the currently running application. The reconfiguration is achieved by inserting multiplexers in the network which allow the cores to dynamically change their position locally in the network. Our approach towards application mapping works in two phases. In the first phase, mapping of the combined core graph (considering all applications) onto the mesh topology is carried out. This is followed by reconfiguration according to the requirements of individual applications for minimizing the communication cost further. We have proposed an exact method based on Integer Linear Programming (ILP) for mapping, as well as for the reconfiguration phase. The reconfiguration phase is independent and thus can be embedded with any mapping algorithm available in the literature. A heuristic has also been developed for the reconfiguration stage. The rest of the paper is organized as follows. Section II gives the literature survey. Section III details our architecture. Section IV details the ILP formulation. Section V contains the proposed heuristic. Section VI enumerates the experimental results. Section VII concludes the paper. II. RELATED WORK A reconfigurable NoC (ReNoC) architecture has been presented in [3] which enables the network topology to be configured for the application running on the SoC by using topology switches. In [4], a reconfigurable NoC architecture has been proposed on which regular and application specific topologies can be implemented according to the application running. In [5], authors have proposed Dynamic Bypass Circuit and north-last weave routing algorithm to realize dynamic reconfigurable NoC. The network reconfigures itself for different applications at run-time. A flexible network design has been proposed in [6] which is scalable and can be changed to accommodate various needs of applications. In [7], authors have proposed a reconfigurable NoC by clustering of cores. They have connected many cores per router which may lead to increase in the complexity and power consumption of the routers. Only one application is taken at a time for mapping onto the reconfigured NoC. Thus, the mapping may not be suitable for other applications running on it. In contrast, in our work, we have considered multiple applications at a time and configured the network according to the application running. Our work is simpler as there is no need to generate a specific topology for each application running on NoC. The proposed approach takes the advantage of using the regular topology of mesh and also satisfies the requirements of different applications running on NoC by changing the positions of the cores locally on the architecture providing reconfiguration. III. OUR APPROACH A. The Reconfigurable NoC Architecture The reconfigurable architecture proposed in this paper is built around the one reported in [7]. Compared to many other topologies [3, 4] that attempt to reduce distance between communicating cores via introduction of configurable switches, this architecture uses multiplexers. The cores have limited choice to get attached to the routers, however, the overall architecture A Locally Reconfigurable Network-on-Chip Architecture and Application Mapping onto it Soumya J., Ashish Sharma, Santanu Chattopadhyay Department of Electronics and Electrical Communication Engineering Indian Institute of Technology Kharagpur, Kharagpur, India soumyaj@ece.iitkgp.ernet.in, ashish.er88@gmail.com, santanu@ece.iitkgp.ernet.in 978-1-4799-4006-6/14/$31.00 ©2014 IEEE