IOSR Journal of VLSI and Signal Processing (IOSR-JVSP) Volume 6, Issue 1, Ver. I (Jan. -Feb. 2016), PP 49-54 e-ISSN: 2319 – 4200, p-ISSN No. : 2319 – 4197 www.iosrjournals.org DOI: 10.9790/4200-06114954 www.iosrjournals.org 49 | Page CMOS Design of Low Power High Speed NP Domino Logic Uday Kumar Rai 1 , Rajesh Mehra 2 , Deepak Rasaily 3 ME Scholar1,3 ,Associate Professor2 Department of Electronics and Communication, National Institute for Technical Teachers Training and Research, Sector -26, Chandigarh, 160019 Abstract : A low cost design and simple to implement, CMOS NP Domino logic is presented. The NP Domino logic designs require fewer transistors and are compatible with full Domino logic. The performance of NP Domino logic is also better compared to the standard Domino logic implementations. Dynamic domino logic are very good but had many challenges like monotonicity, leakage, charge sharing and noise problems. These problems are totally eliminated in the CMOS NP Domino logic (which is also known as Zipper circuits) without any penalty in performance or silicon area utilization. This paper compares NP Domino logic with static CMOS and domino (dynamic) logic design implementations. Keywords - CMOS, NP Domino logic, monotonicity, Zipper, static, I. INTRODUCTION Dynamic CMOS circuits had better performance and require less silicon area than conventional static CMOS circuits. There are various dynamic schemes that had been proposed, Domino CMOS, NORA CMOS pipelined logic structures etc.[1][2]. All these design styles employs a single phase clock to drive their circuit’s gates, exploiting the full inherent speed of the dynamic gates. The dynamic stage of all Domino CMOS is composed of Ν logic and eliminates the internal race conditions by using a buffer at the output of every stage that produces only noninverting signal. This problem is solved in NP Domino (Zipper or NORA)[3] circuits which employ a pipelined structure of NP CMOS and clocked CMOS latches. Since NP Domino circuit has no inverter at the output of each stage, it is generally composed of fewer transistors than Domino CMOS circuits. It also offers more logical flexibility by providing both inverting and noninverting signals at the output. The dynamic Domino CMOS circuits also suffer from signal degradation caused by leakage current and charge redistribution. Many alternative solutions like complex clocking, extra transistors or large buffer[2] have been proposed to solve these problems. In this paper, we introduce a CMOS that incorporates all the advantages of Domino CMOS. NP Domino CMOS are immune to the problems of instability and charge-sharing. The area utilization is also better than the Domino CMOS. In the section that follows, we will describe the dynamic CMOS structure and its features and later deal with the performance of NP Domino CMOS logic circuits [4]. II. LOGIC STYLES The cascading of dynamic logic from one gate to other gives problem. The precharge "1" state of the first gate causes the second gate to discharge prematurely, before the first gate has reached its correct state as shown in Fig. 3. This uses up the "precharge" of the second gate, which cannot be restored until the next clock cycle, thus there is no recovery from this error. The solution to cascade dynamic logic gates is Domino Logic that inserts an ordinary static inverter between the two stages. Although the inverter has a pMOS (one of the main goals of Dynamic Logic is to avoid pMOS where possible, due to speed), there are two reasons it works well. First, there is no fanout to multiple pMOS; the dynamic gate connects to only one inverter, so the gate is still very fast. Furthermore, since the inverter connects to only nMOS in dynamic logic gates, it too is very fast. Secondly in some types of logic gate the pMOS in an inverter can be made smaller.