1580 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 47, NO. 8, AUGUST 2000 Super Thin-Film Transistor with SOI CMOS Performance Formed by a Novel Grain Enhancement Method Hongmei Wang, Mansun Chan, Member, IEEE, Singh Jagar, Vincent M. C. Poon, Member, IEEE, Ming Qin, Yangyuan Wang, Senior Member, IEEE, and Ping K. Ko, Fellow, IEEE Abstract—High performance super TFT’s with different channel widths and lengths, formed by a novel grain enhancement method, are reported. High temperature annealing has been utilized to enhance the polysilicon grain and improve the quality of silicon crystal after low temperature MILC treatment on amorphous silicon. With device scaling, it is possible to fabricate the entire transistor on a single grain, thus giving the performance of single crystal SOI MOSFET. The effects of grain boundaries on device performance have been studied, indicating the existence of extra leakage current paths caused by the grain boundaries traversing the channel, which induced subthreshold hump and early punchthrough of wide devices. The probability for the channel region of a TFT to cover multiple grains decrease signif- icantly when the device is scaled down, resulting in better device performance and higher uniformity. Index Terms—Grain enhancement, thin-film transistor, 3-D VLSI. I. INTRODUCTION T HIN-FILM-TRANSISTORS (TFT’s) inherently have the potential advantages of silicon-on-insulator (SOI) MOSFET’s such as high density, easy isolation, and simple process, as well as the possibility to be used in vertical inte- gration. However, the application of TFT’s is mainly limited to low-temperature flat-panel display due to its substantially worse performance caused by the grain boundaries in the channel region [1], [2]. With the increasing demand for portable system and the pursuance of tera-scale integrated circuits, truly three-dimensional (3-D) device and interconnect technology, which provide a revolutionary breakthrough in circuit compactness, has become an important topic in research [3]. Thin-film-transistor (TFT) technology has been receiving more attention now because it is a promising mean of achieving 3-D integration. It has also been utilized in various 3-D circuits such as SRAM’s and DRAM’s [4]–[7]. Unfortunately, the low on-current, high threshold voltage, and significant device to device variation in conventional polysilicon TFT’s restrain Manuscript received January 21, 2000. This work was supported by a Com- petitive Earmarked Research Grant from Research Grant Council of Hong Kong. The review of this paper was arranged by Editor C.-Y. Lu. H. Wang, M. Chan, S. Jagar, V. M. C. Poon, M. Qin, and P. K. Ko are with the Department of Electrical and Electronic Engineering, Hong Kong University of Science and Technology, Clear Water Bay, Kowloon, Hong Kong (e-mail: mchan@ee.ust.hk). Y. Wang is with the Institute of Microelectronics, Peking University, Beijing, 10087, China. Publisher Item Identifier S 0018-9383(00)06034-2. their further applications in other 3-D structures, especially when device size is scaled down and supply voltage is reduced. It is believed that electrical properties of the TFT’s can be improved if the grain size can be enhanced and the number of grain boundaries in the channel region can be minimized. Single-grainlike TFT’s have been fabricated by solid phase crystallization (SPC) [8] and germanium-seeded laterally crystallization technology [9], [10], but the grain size ( m) is still small compared to the size of the transistor. Thus the performance is still unsatisfactory. Metal-Induced-Lat- eral-Crystallization (MILC) has been studied in the past to obtain large and regular polysilicon grain from amorphous silicon, while keeping the silicon grains mostly free of metal contamination [11], [12]. Despite the considerable grain length obtained by this method, the grain width achieved is limited to less than one micron, which is too small to realize single crystal device with high controllability. In this work, we have discovered that by applying high temperature annealing to amorphous silicon with metal-induced-lateral-crystallization (MILC) treatment, the grain size of the resulting silicon can be significantly enhanced in both grain length and width direction [13], [14]. With device scaling, it is possible to fabricate the entire channel region of a MOSFET in a single grain. Single grain super TFT’s with SOI CMOS performance have been fabricated on these grain-enhanced regions. The super TFT’s technology can be easily integrated into a CMOS technology, without any requirement for extra equipment. The crystalliza- tion and device fabrication process will be briefly described in Section II. In Section III, we will discuss the mechanisms of MILC grain size enhancement at high temperature annealing. We believe that large grain size is caused by the secondary re- crystallization of MILC polysilicon grains, and the thin silicon film with the same grain crystal orientation further enhance the secondary recrystallization. The device characterization will be described in Section IV. It is found that super TFT’s with SOI CMOS performance and good uniformity can be obtained through the reduction of the channel dimensions. The influence of grain boundaries on device performance will also be discussed in this section. Finally, Section V will give a conclusion on the results obtained. II. CRYSTALLIZATION AND DEVICE FABRICATION The formation of super TFT’s with enhanced grain started by growing 3000 Å of oxide on normal silicon wafer to serve 0018–9383/00$10.00 © 2000 IEEE