Improving MOSFETs Radiation Robustness by using the Wave Layout to Boost Analog ICs Applications Rafael Navarenho de Souza I , Student Member, IEEE, Marcilei A. Guazzelli da Silveira 2 , Member, IEEE and Salvador Pinillos Gimenez l , Member, IEEE. I Department of Electrical Engineering, Centro Universitario da FE!, Sao Bernardo do Campo, Sao Paulo, Brazil 2 Department of Physics, Centro Universitario da FE!, Sao Bernardo do Campo, Sao Paulo, Brazil E-mail: rafaelnds@gmai1.com Abstract - This paper describes an experimental comparative study of the total ionizing dose (TID) effects between the Metal Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFET) manufactured with the Wave (S gate geometry) and the standard layouts (CnM). Because of the special characteristic of the bird's beaks regions of the Wave MOSFET WnM), this innovative layout proposal for transistors is able to increase the devices TID hardness for analog integrated circuits (IC) applications in terms of the unity voltage gain frequency (fT) without causing any additional cost to the Complementary MOS (CMOS) manufacturing process. Kywords- Wave layout, radiation hardness by design, total ionizing dose, TID, analog circuits, unit voltage gain frequency. I. INTRODUCTION The Total Ionizing Dose (TID) effects produce long-term damage within the oxide layers of the electronic devices, worsening the electrical performance of MOSFET [1]. New materials, multiple-gates and three-dimensional (3D) devices are the subject of intense research and development [1], following the Intenational Technology Roadmap for Semiconductor (ITRS) [2] speciications for uture technologies and devices, in order to overcome the scaling limits [3-5]. Many efforts have been made to improve the devices radiation hardness, which mainly can be divided in two categories. One category is related to the optimization of manufacturing process with different materials and technologies [2], the other one focuses on using non-standard layout for MOSFET [4]. Several techniques have been investigated to reduce the TID effect, one way is to extend and overlap the gate oxide to the lateral isolation region of the MOSFET [6], like in the Shallow Trench Isolation (STI) technologies where similar method can be applied by pulling back the source and drain regions rom the trench edges [7]. Another proposal is the use of Silicon-On-Insulator (SOl) wafer that isolates the substrate of the operation active region of MOSFET with a buried oxide (BOX) to reduce the power dissipation, the latch-up, the short channel effects (SCE), and the single event effects (SEE) [S]. However, the thick BOX in SOl MOSFET substrates increases the undesired TID effects in these devices, because the ionizing radiation induces positive charges to be trapped in BOX [9, 10]. 978-1-4799-4696-9/14/$31.00 ©2014 IEEE The Multiple-Gates Field Effects Transistors (MugFET) have been studied and indicated to be one of the most promising devices to meet the downscale, although they have been presented a few years ago, with the issue of the FinFET concept to replace the planar CMOS technology [11]. In order to meet the downscaling, especially in the sub 20- nm node, the planar ultrathin buried oxide (UTBOX) and thin body SOl (UTB) technologies have been considered as an altenative to replace the Bulk substrate technology [12], in order to reduce the SCE and the random dopant luctuations (RDF) [13]. Besides that, the use of the UTBOX enables a low-power multi-threshold-voltage operation by the use of the back-gate bias [14], even though the UTBOX exhibits a signiicant shiting range of the threshold voltage (VTH), these devices are able to mitigate the TID effects, due to its stronger capacitive coupling effects [15]. Although, the gate oxide becomes thinner and less sensitive to the TID effect, MOSFET manufactured with the Shallow Trench Isolation (STI) is not scaled down in the same proportion to the device size and because of that limits the ionizing radiation tolerance in the Bulk CMOS technology (radiation induced positive charge to be trapped in the STI) [16]. All of these techniques previously considered generate a high cost impact of the CMOS manufacturing process. Besides that, the use of Hardness By Design (HBD) enables the improvement of the device radiation hardness [16], a very eicient way is to use Enclosed Layout Transistors (ELT), which completely eliminated the parasitic leakage path of the drain current (IDS) [17]. The ELT is "edgeless", for instance, an annular gate region completely surrounding the drain region, which in turn it is surrounding by the source region [IS]. This approach shows to be very effective, enabling the MOSFET to present TID tolerances in multi Mrad scale, [19-20]. The disadvantages for using this approach are the die area and capacitance increase, and the aspect ratio (WIL) limitations [21-23], despite the fact that the ELT is inherently asymmetric [24]. A number of variations of the ELT have also been developed to alleviate those shortcomings to some level [25], although, they do not reduce the die area and change the manufacturing process.