XVII SIM - South Symposium on Microelectronics 1 Modeling of Embedded Digital Systems from SDL Language: a Case Study César A. M. Marcon, Fabiano P. Hessel, Alexandre M. Amory, Luís H. L. Ries, Fernando G. Moraes, Ney L. V. Calazans {marcon, hessel, amory, ries, moraes, calazans}@inf.pucrs.br Abstract The goal of this paper is to evaluate the performance of digital systems generated from a high-level description language. The target language in this work is SDL. The SDL description is automatically synthesized with a codesign tool, resulting in a VHDL description. The codesign tool is responsible for software, hardware and communication synthesis. The presented results concerns only the hardware synthesis, since the goal is to compare the performance of systems generated from manual VHDL descriptions against a synthesized VHDL. Two case studies are presented, exploring area and delay results. 1 Introduction Embedded systems requirements are getting increasingly complex. This complexity requires modern design methodologies to prototype such systems in a competitive time-to-market. In general, embedded systems are constructed with hardware and software parts, leading to a design environment implementing the hardware and software concomitant design, or just codesign. Coware n2c [1], Ptolemy [2] and Seamless [3] are typical environments supporting such a codesign scheme. These environments start from a system-level specification with languages like SDL, C/C++/SystemC, Esterel and Java. Figure 1 shows a typical codesign flow. The flow starts with an informal specification of the whole system, generally in natural language. This specification forms the basis for analyzing the system requirements and for the high-level description of the system functionality. From the informal specification a first high-level formal description is generated. This description depicts systems functionality, in most cases, as a hierarchical mixed data/control flow diagram, and can be written in one of the above-cited languages. System-level simulation or formal verification achieves validation and exploration of algorithms and systems functionality. Formal system specification Hardware description Software description Formal verification Behavioral simulation Software synthesis Hardware synthesis Interface synthesis Memory and processor implementation Hardware components implementation Compilation Physical synthesis System description (internal format) Scheduling and partitioning Constraint analysis and communication refinement Informal system specification Requirements and functionality’s extraction RTL Hardware description Target soft. description Functional co-simulation RTL co-simulation Physical co-simulation (back annotated) Figure 1 – Hardware/software integrated design flow. The second step consists in the refinement of high-level inter-module communication, including protocol selection. Some design alternatives are examined to identify those that meet the system constraints, and the architectural choices are made, generally guided by the user. Once architecture is decided, the functional specification is mapped into an abstract architectural model. This model may include one or more processors and others components. At this stage, the system can be viewed as technology independent multiprocessor architecture mixed with hardware components.