Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers Hamed Aminzadeh a,n , Mohammad Danaie b , Wouter A. Serdijn c a Department of Electrical Engineering, Payame Noor University, 19395-3697 Tehran, Iran b Faculty of Electrical and Computer Engineering, Semnan University, Semnan, Iran c Electronics Research Laboratory, Delft University of Technology, Delft 56101, The Netherlands article info Article history: Received 29 March 2013 Received in revised form 2 August 2013 Accepted 6 August 2013 Keywords: Cross-feedforward cascode compensation Frequency compensation Hybrid cascode feedforward compensation Low power Nested-Miller compensation Operational amplifier (opamp) Single-Miller feedforward compensation and stability abstract A modified frequency compensation technique is proposed for low-power area-efficient three-stage amplifiers driving medium to large capacitive loads. Coined hybrid cascode feedforward compensation (HCFC), the total compensation capacitor is divided and shared between two internal high-speed feedback loops instead of only one loop as is common in prior art. Detailed analysis of this technique shows significant improvement in terms of bandwidth and stability. This is verified for a 1.2-V amplifier driving a 500-pF capacitive load in 90-nm CMOS technology, where HCFC reduces the total capacitor size and improves the gain-bandwidth by at least 30% and 40% respectively, compared to the prevailing schemes. & 2013 Elsevier Ltd. All rights reserved. 1. Introduction Frequency compensation is a conventional design step in the design procedure for negative-feedback amplifiers used in drivers, filters, data converters and low-dropout regulators [1–17]. Depend- ing on the load capacitor (C L ), a minimum compensation capacitor (C C ) is required to maintain stability, by which the gain-bandwidth (GBW) and slew-rate (SR) are affected depending on their value. With two large compensation capacitors proportional to C L , the well-known nested Miller compensation (NMC) [1–3] fails to achieve sufficient GBW and SR under low power constraints. Various frequency compensation strategies have therefore been proposed to reduce the size of the compensation capacitors with limited power budget. Multipath nested Miller compensation (MNMC) [6] compen- sation is among these solutions which aims to further push away the power/area envelope. It uses a feedforward stage to implant an additional left-half-plane (LHP) zero to the NMC transfer function. The undesired right-half plane (RHP) zero in basic NMC architecture imposes excessive power for sufficient stability. Nested Gm-C com- pensation is another compensation solution dedicated for three- stage amplifiers to remove this RHP zero [7]. Looking for ways to remove the bulky capacitance used within the internal ac feedback loop of the NMC has also been the idea of some improved architectures. This capacitance is used to control the location of the complex poles for adequate gain margin (GM). The damping-factor- control frequency compensation (DFCFC) [8] replaces this capacitor with an active damping-factor-control unit. As a step further, the main compensation capacitor is substituted with an active capaci- tance in active feedback frequency compensation (AFFC) [9], resulting in improved stability with lower compensation capacitance. The remaining passive capacitance in AFFC is replaced by a damping- factor-control unit in dual-loop parallel compensation (DLPC) [10]. Two high-speed paths are also included to extend the bandwidth and to reduce the capacitor [10]. A serial RC network is added at the output of the amplifier intermediate stage to create a LHP zero in impedance adapting compensation (IAC) [11]. A standard Miller capacitance is also used for pole-splitting. Combining the concepts of signal feedforwarding and pole-splitting, single Miller capacitor feedforward frequency compensation (SMFFC) successfully removes the second compensation capacitance in NMC topology [12]. As proposed, the sizing of the remaining capacitance can also be decreased when increasing the gain of the intermediate stage [12]. To stabilize the amplifiers driving ultra-large capacitive loads, a few compensation techniques have been reported so far. Among these solutions are single capacitor with current amplifier compen- sation (SCCAC) [13], and current-buffer Miller compensation (CBMC) plus parasitic-pole cancellation [14,15]. Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/mejo Microelectronics Journal 0026-2692/$ - see front matter & 2013 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.mejo.2013.08.004 n Corresponding author. E-mail addresses: haminzadeh@ieee.org, h.aminzadeh@pnum.ac.ir (H. Aminzadeh), danaie@profs.semnan.ac.ir (M. Danaie), w.a.serdijn@tudelft.nl (W.A. Serdijn). Please cite this article as: H. Aminzadeh, et al., Hybrid cascode feedforward compensation for nano-scale low-power ultra-area-efficient three-stage amplifiers, Microelectron. J (2013), http://dx.doi.org/10.1016/j.mejo.2013.08.004i Microelectronics Journal ∎ (∎∎∎∎) ∎∎∎–∎∎∎