A Crosstalk-and-ISI Equalizing Receiver in 2-Drop Single-Ended SSTL Memory Channel Jun-Hyun Bae 1 , Young-Soo Sohn 2 , Seung-Jun Bae 2 , Kwang-Il Park 2 , Joo-Sun Choi 2 , Young-Hyun Jun 2 , Jae-Yoon Sim 1 , and Hong-June Park 1 1 POSTECH, DEP. EE., POHANG, KOREA 2 SAMSUNG ELECTRONICS, CO., LTD., HWASEONG, KOREA Abstract-An equalizer circuit which minimizes both crosstalk and ISI is applied to a receiver with a strongly-coupled 2-parallel 2- drop single-ended microstrip SSTL memory channel. The crosstalk equalizer adds a crosstalk-canceling pulse to a victim receiver signal to make the signal crosstalk-free during the transition interval of an incoming signal. A DFE is used for ISI compensation. The equalization of both crosstalk and ISI increases the data rate for BER < 1E-12 from 2.5Gbps to 3.6Gbps with a 0.18μm CMOS process. I. INTRODUCTION A performance bottleneck of a computing system is a limited interface data bandwidth between processor and memory. To increase the interface data bandwidth under a limited channel bandwidth, a multi-bit parallel interface is widely used in the memory interface. To increase the available memory capacity, a multi-drop structure is generally used in the main memory. However, the high-speed data transmission along parallel lines induces the crosstalk at the receiving ends. This crosstalk generates a crosstalk-induced jitter (CIJ), and reduces the timing margin of the data eye at the receiver [1][2][3]. The multi-drop interface structure causes a large inter-symbol interference (ISI) due to an increased chip loading, and reduces the timing and voltage margins of the data eye at the receiver [4]. These CIJ and ISI degrade the BER of an overall transmission system. Works ([1] and [2]) are published to reduce CIJ. A crosstalk equalizer at receiver [1] used an analog mode detection circuit and an analog delay line, and was applied to an ISI-free channel. Another crosstalk equalizer at transmitter used a digital mode detection circuit and adjusted the data time at transmitter to compensate for CIJ [2]. In this work, an equalization scheme is proposed for receiver, which compensates both crosstalk and ISI. Neither the crosstalk mode detection circuit nor the analog delay line is used in this work. II. PROPOSED CROSSTALK EQUALIZATION SCHEME In a 2-parallel coupled channel (Fig. 1), the far-end crosstalk voltage waveform V FEXT (t) with an aggressor signal V 2 (t) can be expressed as, ( ) 2 () 2 f f m m FEXT T S dV t t t C L V t C L dt - ⎛ ⎞ = ⋅ - ⋅ ⎜ ⎟ ⎝ ⎠ (1) Z 0 V 2 (t) Z 0 Z 0 Z 0 CH2 : Aggressor CH1 : Victim V2(t-tf) V FEXT (t) (a) V 2 (t-t f ) V FEXT (t) (b) Fig. 1 (a) 2-coupled microstrip line (b) Far-end crosstalk 0 0 0 CH2 : V 2 (t-t f ) CH1 : V FEXT (t-t f ) V CCP (t-t f ) + τ 0.5T CH1 V FEXT (t-t f ) + V CCP (t-t f ) VL -VXT VXT VXT VH (a) 0 CH2 : V 2 (t-t f ) CH1 : V 1 (t-t f ) V CCP (t-t f ) + τ 0.5T CH1 V 1 (t-t f ) + V CCP (t-t f ) VL VL-VXT VXT VH VL VH VH-VXT VL VH VL+VXT VH+VXT (b) Fig. 2 Principle of the proposed crosstalk equalization scheme (a) No signal applied at victim (CH1) (b) Rising pulse applied at victim (CH1) 978-1-4244-5759-5/10/$26.00 ©2010 IEEE