Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits Hassan Mostafa, M. Anis, and M. Elmasry Department of Electrical and Computer Engineering, University of Waterloo, Waterloo, ON, Canada N2L3G1 {hmostafa@uwaterloo.ca, manis@vlsi.uwaterloo.ca, elmasry@uwaterloo.ca } Abstract—In synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Moreover, the process variations create a large variability in the flip-flop delay in scaled technologies impacting the timing yield. Overtime, many gate sizing algorithms have been introduced to improve the timing yield. This paper presents an analysis of timing yield improvement of four commonly used flip- flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip- flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has a power overhead and PDP overhead of 1.7X and 2.8X, respectively, much higher than that of the transmission-gate master-slave flip flop (TG-MSFF) . The TG-MSFF exhibits the lowest relative power and PDP overheads of 30.87% and 9% ,respectively. I. I NTRODUCTION As CMOS technologies continue to scale towards the nanometer regime, the device parameters, such as threshold voltage, channel length, oxide thickness and mobility, will have large statistical process variations [1-5]. Consequently, these process variations will lead to delay uncertainty. There- fore, the deterministic design methodology is replaced by the statistical design methodology [6]. The process variations can be classified as die-to-die (inter-die) variations or within-die (intra-die) variations. In die-to-die variations, all devices on the same die are assumed to have the same parameters. However, devices on the same die are assumed to behave differently for within-die variations [1]. Although die-to-die variations were originally considered as the main source of process variations, within-die variations have now become the major design challenge as technology scales [3,4]. Moreover, the demand for higher performance has moved the clock frequen- cies up to multi-GHz in microprocessors and other advanced applications. These increased clock frequencies lead to very deep pipelining which means that hundreds of thousands of flip-flops are required to control the data flow under strict timing constraints. A violation of the timing constraints at a flip-flop can result in latching incorrect data causing the overall system to malfunction [7]. Deterministic gate sizing tools size the circuits to optimize the power-delay-product (PDP). However, due to random process variations, a large number of circuits might not meet the target delay. Consider as an intuitive example, a flip-flop that is designed for optimum PDP, which exhibits a specific target delay. Due to random process variations, the delay can be modeled by a normal distribution with the probability density function (pdf) shown in Figure 1. Here, 50% of the total number of flip-flops will not meet the desired target delay constraint. Therefore, the flip-flops must be designed by using statistical sizing tools to improve the timing yield [8, 9]. In [10], a comparative analysis of the impact of the process variations on flip-flops power and delay is introduced. However, the analysis utilizes deterministic sizing tools to size the flip-flops, resulting in a poor timing yield (less than 50%). Therefore, the utilization of statistical sizing tools for timing yield improvement is more appropriate for an efficient and fair comparison, since the timing yield is the main concern in high performance applications. This paper provides a comparative analysis of timing yield improvement under process variations of four different flip-flops topologies, especially for the delay variability and the required power and PDP overheads for timing yield improvement. These flip-flops represent different trade-off choices between performance and power dissipation. The paper is organized as follows: Section 2 introduces the selected flip-flops designs and summarizes the flip-flops timing characteristics. Sections 3 and 4 describe the simulation setup and the simulation results, respectively. Finally, some conclusions are drawn in Section 5. Fig. 1. The delay pdf due to process variations under deterministic gate sizing algorithms. It shows, intuitively, that up to 50% of flip flops will not meet the target delay (50 ps in this example) 2009 IEEE Computer Society Annual Symposium on VLSI 978-0-7695-3684-2/09 $25.00 © 2009 IEEE DOI 10.1109/ISVLSI.2009.23 133 Authorized licensed use limited to: University of Waterloo. Downloaded on September 14, 2009 at 23:49 from IEEE Xplore. Restrictions apply.