2342 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 39, NO. 12, DECEMBER 2004 A 4- A Quiescent-Current Dual-Mode Digitally Controlled Buck Converter IC for Cellular Phone Applications Jinwen Xiao, Student Member, IEEE, Angel V. Peterchev, Student Member, IEEE, Jianhui Zhang, Student Member, IEEE, and Seth R. Sanders, Member, IEEE Abstract—This paper describes a dual-mode digitally controlled buck converter IC for cellular phone applications. An architecture employing internal power management is introduced to ensure voltage compatibility between a single-cell lithium-ion battery voltage and a low-voltage integrated circuit technology. Special purpose analog and digital interface elements are developed. These include a ring-oscillator-based A/D converter (ring-ADC), which is nearly entirely synthesizable, is robust against switching noise, and has flexible resolution control, and a very low power ring-oscillator-multiplexer-based digital pulse-width modulation (PWM) generation module (ring-MUX DPWM). The chip, which includes an output power stage rated for 400 mA, occupies an active area 2 mm in 0.25- m CMOS. Very high efficiencies are achieved over a load range of 0.1–400 mA. Measured quiescent current in PFM mode is 4 A. Index Terms—Analog–digital conversion, CMOS integrated circuits, dc–dc power converstion, digital–analog converstion, digital control, digital pulse-width modulation (DPWM), pulse frequency modulation, pulse-width-modulated power converters, pulse-width modulation (PWM), ring ADC, ring-MUX DPWM. I. INTRODUCTION T HIS paper presents an ultralow-quiescent-power dual-mode digitally controlled buck converter IC for cellular phone applications. While the cellular phone is in talk mode, the load on the buck converter is high and pulse-width modulation (PWM) is used to achieve high regulation quality as well as high efficiency. However, when the cellular phone is in standby mode, in which the load current is very low, PWM mode leads to low efficiency due to excessive switching, gate drive, and quiescent current losses. To extend the standby time a cellular phone can sustain with each full charge of the battery, pulse frequency modulation (PFM) mode is preferred for light load operation. The designed IC supports PWM mode for heavy loads and PFM mode for light loads. The system block diagram of the buck converter IC and the external filter is shown Manuscript received March 6, 2004; revised June 21, 2004. This work was supported by Linear Technology Corporation, Fairchild Semiconductor, Na- tional Semiconductor, the University of California MICRO program, and the National Science Foundation under Contract ECS-0323615. J. Xiao is with Silicon Laboratories, Austin, TX 78735 USA (e-mail: jixiao@silabs.com). A. V. Peterchev, J. Zhang, and S. R. Sanders are with the Department of Elec- trical Engineering and Computer Science, University of California, Berkeley, CA 94720 USA (e-mail: sanders@eecs.berkeley.edu). Digital Object Identifier 10.1109/JSSC.2004.836353 in Fig. 1. The pin MODE is used to switch between the two modes. The PFM-mode quiescent power is the fundamental limitation on light-load efficiency, and, in this study, an ultralow quiescent current of 4 A is achieved in PFM mode. Details of the dual-mode design are presented in Section II. For a digital implementation, small feature size processes with low supply voltages are preferred for implementing the dig- ital circuits to achieve small die area, high speed, and low power consumption. In cellular phone applications, the power supply of the buck converter system is usually a single-cell lithium-ion battery, with voltage range of 2.8–5.5 V. Thus, the input voltage of the converter may be higher than the allowed supply voltage of the process (e.g., a maximum 2.75 V for a 0.25- m CMOS process). A solution that allows a low-voltage process to be used for the digital controller with high input voltage can be of great interest considering the possible cost reduction from integrating the switching regulator on the same die with the power train de- vices. Internal power management is introduced to resolve the conflict of high input voltage and a low-voltage process, the de- tails of which are also presented in Section II. The analog-to-digital converter (ADC) and the digital pulse-width modulator (DPWM) are used to provide the inter- face between the digital compensation network and the analog power train. A general purpose ADC can be unnecessarily expensive in terms of both power consumption and chip area; therefore, a ring-oscillator-based averaging ADC (ring-ADC) is developed which has reduced the quantization range. The details of the ADC are presented in Section III. The DPWM runs in both PWM and PFM modes, and thus low power is a primary design objective for this block. A very low-power DPWM scheme based on a ring-oscillator-multiplexer structure (ring-MUX DPWM) is developed, the details of which are presented in Section IV. A prototype IC takes an active area of 2 mm in a 0.25- m CMOS process. With a cascode power train and internal power management, the IC demonstrates safe operation of a standard CMOS process rated for 2.75 V with a 5.5-V supply. The power train on the chip is rated for a 400-mA load current, and effi- ciency above 90% is achieved for a load range of approximately 50–300 mA under PWM operation. Efficiency above 70% is achieved over the load range of 0.1–400 mA in PFM mode. The latter result is enabled by a 4- A quiescent current in PFM mode. Further experimental results are detailed in Section V. 0018-9200/04$20.00 © 2004 IEEE