The Performance-Energy Tradeoff in Embedded Systems Design: A Survey of Existing Design Space Exploration Tools and Trends Manel Ammar, Mouna Baklouti, and Mohamed Abid CES Laboratory National Engineering School of Sfax Sfax, Tunisia Email: manel.ammar@ceslab.org Abstract—The complexity and computational requirements of Intensive Signal Processing (ISP) applications require rising performance while maintaining energy effectiveness. However, the energy efficiency wall creates a large gap between current processing capabilities of many-core systems and computational requirements of ISP applications, indicating the beginning of a new era, where advance is measured by improvements in transistor energy efficiency. In this context, the concept of energy- aware Design Space Exploration (DSE) has begun to spread in the past few years, gaining increasing popularity. This article presents a survey of DSE tools and methodologies that targets either performance optimization, or energy optimization, or both. This survey aims at identifying strengths and weaknesses of actual directions in the Electronic Design Automation (EDA) industry to build solid energy-aware DSE tools. I. I NTRODUCTION At the beginning of this new century, the rapidity of information growth goes beyond the evolution of Moore’s Law. Accordingly, massive data including signals are making big pressure on the digital signal processing field leading to the emergence of new discipline: Intensive Signal Processing (ISP). At the present time, many-core systems are commonly dedicated to ISP applications where huge amounts of data are handled in a regular way by means of repetitive computations. As performance presents an important feature of emerging many-core systems, the design of such systems should meet strict time-to-market and cost constraints, while holding the guarantee of rising performance through parallelism. Performance relies on a diverse set of factors and parame- ters. Design Space Exploration (DSE) means adjusting these factors and parameters while taking into account a set of metrics (execution time, latency, throughput, etc.) to find the optimal combination between the many-core architecture and the ISP application at an early phase of the system design. Research on the DSE of modern applications running on complex System-on-chip (SoC) is still emerging. As the speed metric of many-core systems has increased over time, an- other metric has become more important: power consumption. Power and energy efficiency must now be added to the performance metrics of embedded systems, making perfor- mance per watt the new metric of merit. Consequently, power consumption becomes a key criterion to take into consideration during DSE. Finding a tradeoff between power consumption and performance early in the design flow in order to satisfy time-to-market is the design challenge of Electronic Design Automation (EDA) tools. The shift from a performance-aware to an energy-aware, centric DSE focus, poses many design challenges for the EDA community. To overcome these challenges, this article paints the DSE tools landscape by revising DSE tools dealing with performance and timing optimization of embedded systems; and studying energy-aware DSE tools making a tradeoff be- tween performance and energy. This survey should help EDA designers to build DSE tools more efficiently. Authors in [1], identify two main approaches to DSE: simulation-based and analytical-based approaches. We use this paradigm to classify several DSE-related tools. The rest of this article is organized as follows. Section II discusses the design challenges of modern embedded systems. Section III and IV provide taxonomy of recent literature for performance-aware and energy-aware DSE approaches, and review the main proposals for each approach. Each section compares and discusses these approaches. Finally, we con- clude the article in Section V. II. DESIGN CHALLENGES Designers of many-core embedded systems executing ISP applications are facing many design challenges. Challenges can be either associated with hardware development or with software development or with both of them. A. The utilization wall: performance versus energy efficiency For the past three decades, Moore’s law [2] coupled with Dennard scaling [3], have been two fundamental drivers of computing, resulting in exponential performance increases. Dennard scaling claims that while transistors get smaller, along the lines of Moore’s law; their power density stays constant. This is strongly attached to Koomey’s law, which states that performance per watt would double every 1.57 years [4]. International Journal of Computer Science and Information Security (IJCSIS), Vol. 14, No. 5, May 2016 381 https://sites.google.com/site/ijcsis/ ISSN 1947-5500