IEEE TRANSACTIONS ON COMPUTERS, VOL. C-22, NO. 11, NOVEMBER 1973 Complete Test Sets for Logic Functions SUDHAKAR M. REDDY Abstract-The problem of designing fault detecting test sets from the functional description rather than the structural description of the networks realizing the logic function is studied. The concept of an expanded truth table for logic functions is introduced. It is proved that the set of minimal true vertices and maximal false vertices of the expanded truth table constitutes a test set to detect any number of stuck-at-faults in a network belonging to a class of restricted net- works, called unate gate networks. It is further indicated that even in the presence of redundancies in the network, the test sets given remain valid. Index Tenns-Complete test sets, expanded truth table, fault detect- ing test sets, logic networks, multiple stuck-at-faults, restricted gate networks, stuck-at-faults, unate gate networks. I. INTRODUCTION SOLUTIONS to the problem of designing test sets to de- tect faults in an arbitrary realization of a logic function are extremely important, since, normally attempts to derive test sets for a given realization are unwieldy. Also, the given realization may have redundancies in it that might cause the test sets to become invalid [2]. An elegant solution to this problem has been given by Betancourt [1] for the case of unate functions, where the networks realizing these functions are allowed to have a single permanent stuck-at-zero (s-a-0) or stuck-at-one (s-a-i) fault. In this paper we extend Betancourt's [1] result to multiple stuck-at-faults and arbitrary logic functions.1 The important difference between the work reported now and the work re- ported in [6] and [7] is that we do not assume that the actual network realizing a function is known. For the sake of completeness and ease in reading, we will give several definitions and develop a certain amount of nota- tion in this section. Notation f n-variable logic function. F Network realizingf that is being tested for faults. u Unate function. X, Y, etc. Input vectors (vertices). X True vertex off if f(X) = 1. X False vertex off if (X) =0. Xi Input variable. xl Input literal, which is xi or xi (complement of xi). Manuscript received October 8, 1972; revised December 26, 1972. This work was supported in part by the Office of Naval Research Grant N00014-68-A-0500 and in part by NSF Grant GK-36377. The author is with the Department of Electrical Engineering, Uni- versity of Iowa, Iowa City, Iowa 52240. 'Some of the results given in this paper were independently ob- tained by Akers [8] . We will indicate these in the paper. xi xj Network N f S L.2_ of AND/OR Gates '2 ir iI Fig. 1. Restricted gate network realizing f. Fig. 2. Restricted gate network realizing g. Definition 1: A logic function f is positive unate in literal x4 if for every input vector X, such that f(X) = 1, with xi taking the value to make x4 = 0, also implies f(Y) = 1 where Y is obtained by complementing the value of xi in X. If a function is not positive unate in xi or xi, then it is not unate in xi. If f is positive unate in xl, then f is not positive unate in i*. (We are assuming that f is not independent of xi.) Definition 2: A logic function f is a positive unate function of literals x7, 42- , ix* if it is positive unate in xi 1 < j < Q. Notice that this definition of a positive unate function differs from the usual definition, which is given in terms of input variables. Definition 3: A logic network constructed from AND, OR, NAND, NOR, and NOT gates is callQd a gate network. If only AND and/or OR gates are used and inverters, if necessary, are used at the external inputs to gates, then it is called a re- stricted gate network. A block diagram of a general restricted gate network, for a logic function f that is not unate in variables x;, , xj2, , x, and is positive unate in literals XI1, X12, * * *,xr, is given in Fig. 1. The function g = ab + ac + a7d + ac realized by a restricted gate network is given in Fig. 2. Definition 4: If the network N of Fig. 1 is realized by a 1016