228 IEEE ELECTRON DEVICE LETTERS, VOL. 31, NO. 3, MARCH 2010 High-Performance Polycrystalline Silicon TFT on the Structure of a Dopant-Segregated Schottky-Barrier Source/Drain Sung-Jin Choi, Jin-Woo Han, Sungho Kim, Dong-Il Moon, Moongyu Jang, and Yang-Kyu Choi Abstract—A high-performance polycrystalline silicon (poly-Si) thin-film transistor (TFT) with Schottky-barrier (SB) source/drain (S/D) junctions is proposed. A p-channel operation on the intrinsic nickel (Ni) silicided S/D was successfully realized with the aid of a thin active layer, despite the fact that the Ni silicided mate- rial shows a high SB height (SBH) for holes. Furthermore, for n-channel operation, the dopant-segregation technique imple- mented on the intrinsic Ni silicide was utilized to reduce the effec- tive SBH for electrons. The results show a higher on-current due to the lower parasitic resistance as well as superior immunity against short-channel effects, compared to the conventional poly-Si TFT composed of p-n S/D junctions. Index Terms—Dopant-segregated Schottky barrier (DSSB), dopant segregation (DS), high performance, MOSFET, Ni silicide, Schottky barrier (SB), thin body, thin-film transistors (TFTs). I. I NTRODUCTION P OLYCRYSTALLINE silicon (poly-Si) thin-film transistors (TFTs) have been widely used to integrate driver circuits for active-matrix liquid crystal displays and active-matrix or- ganic light-emitting-diode displays due to their higher field- effect mobility and driving current compared to other structures of a TFT [1], [2]. In order to integrate peripheral driving circuits on a glass substrate, a low-temperature process (∼ 600 ◦ C) that does not compromise the device performance should be developed. The constraint of a low process temperature re- sults in low throughput and low activation efficiency due to long-term post-ion-implantation annealing (at ∼ 600 ◦ C for 12–24 h) [3], [4]. The use of a thinner active layer to obtain a higher driving current, a lower off-state leakage current (I off ), and superior immunity against short-channel effects is attractive for poly- Si TFTs as it enables various functional devices such as logic, Manuscript received November 9, 2009; revised November 24, 2009. First published January 26, 2010; current version published February 24, 2010. This work was supported in part by the Nano R&D Program through the National Research Foundation (NRF) of Korea funded by the Ministry of Education, Science and Technology under Grant 2009-0082583 and in part by the Basic Science Research Program through the NRF of Korea funded by the Ministry of Education, Science and Technology (R11-2007-045-03004-0). The review of this letter was arranged by Editor J. K. O. Sin. S.-J. Choi, J.-W. Han, S. Kim, D.-I. Moon, and Y.-K. Choi are with the Division of Electrical Engineering, School of Electrical Engineering and Com- puter Science, Korea Advanced Institute of Science and Technology, Daejeon 305-701, Korea (e-mail: sjchoi@nobelab.kaist.ac.kr; jinu0707@nobelab.kaist. ac.kr; kkam226@nobelab.kaist.ac.kr; dimun@nobelab.kaist.ac.kr; ykchoi@ee. kaist.ac.kr). M. Jang is with ETRI, Daejeon 305-700, Korea (e-mail: jangmg@etri.re.kr). Color versions of one or more of the figures in this letter are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/LED.2009.2038348 memory, and controller devices. Hence, the poly-Si TFTs with a thin active layer can be integrated into the 3-D circuits or mul- tilayer Si ICs for the applications of system on chip and system on panel on a glass panel [5], [6]. However, the employment of a thin active layer inevitably degrades the device performance as a result of a high parasitic resistance (R para ) of the source/drain (S/D) region. In order to reduce R para , various techniques such as a raised S/D structure have been proposed [7], [8]. However, the complex process remains a fatal weakness. Schottky-barrier (SB)-type devices replacing the impurity- doped S/D, i.e., a p-n junction, with a metallic junction have numerous advantages. These include their simple process, low process temperature (less than 400 ◦ C), low R para , strong immunity against short-channel effects, and their inherent phys- ical scalability to a sub-100-nm gate length (L g ) [9], [10]. In addition, for further improvement of SB-type devices, the development of a dopant-segregated SB (DSSB) device with an inserted layer of high-dose dopants at the interface between the metallic silicide and the channel was recently reported. It has been applied to various logic and memory devices on single- crystalline substrates [11], [12]. This letter demonstrates a high- performance poly-Si TFT with a thin active layer at a thickness of 20 nm. This work employs both a p-channel poly-Si SB TFT and an n-channel poly-Si DSSB TFT with various ranges of L g , containing nickel (Ni) silicided S/D junctions. II. FABRICATION A (100) bulk Si wafer is used as a starting material. First, a SiO 2 layer is thermally grown on a silicon substrate at a thickness of 5 nm (a thin buried oxide layer). A thin amorphous silicon layer with a thickness of 20 nm is then deposited and recrystallized in a solid-phase crystallization process at 600 ◦ C for 24 h in N 2 ambient. After patterning the active region, a gate oxide of 5 nm is thermally grown, and n + in situ poly-Si gate is sequentially deposited and patterned. In the n-channel TFT, the dopant-segregation (DS) technique is employed by implanting arsenic ions with a shallow energy of 3 keV at a dose of 5 × 10 15 /cm 2 into the S/D region. A revamped two-step annealing process (first step: 250 ◦ C and second step: 400 ◦ C) involving rapid thermal annealing (RTA) was then utilized for the Ni silicidation of spacer-free DSSB TFTs. This optimized the process and led to a significant reduction of the R para value. In contrast, Ni silicidation without a DS technique was also employed with the same two-step annealing process. After the silicidation process, unreacted Ni is removed using a mixed solution of hydrosulfide and hydroperoxide (H 2 SO 4 : H 2 O 2 = 1 : 1, 10 min). Conventional poly-Si TFTs with a p-n junction 0741-3106/$26.00 © 2010 IEEE Authorized licensed use limited to: Korea Advanced Institute of Science and Technology. Downloaded on March 01,2010 at 03:44:42 EST from IEEE Xplore. Restrictions apply.